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  1. 01 Jul, 2016 2 commits
  2. 31 Mar, 2016 1 commit
    • Stefan Agner's avatar
      clk: imx: clk-gate2: allow custom gate configuration · 45682922
      Stefan Agner authored
      The 2-bit gates found i.MX and Vybrid SoC support different clock
      configuration:
      
      0b00: clk disabled
      0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
      0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
      0b11: clk enabled in RUN and WAIT mode
      
      For some clocks, we might want to configure different behaviour,
      e.g. a memory clock should be on even in STOP mode. Add a new
      function imx_clk_gate2_cgr which allow to configure specific
      gate values through the cgr_val parameter.
      Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      45682922
  3. 02 Mar, 2016 1 commit
  4. 25 Sep, 2015 1 commit
  5. 03 Jun, 2015 5 commits
  6. 05 Jan, 2015 1 commit
  7. 22 Nov, 2014 1 commit
  8. 15 Sep, 2014 1 commit
    • Shawn Guo's avatar
      ARM: imx: add an exclusive gate clock type · 19d86344
      Shawn Guo authored
      There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
      LVDSCLK1_IBEN and LVDSCLK1_OBEN.  They cannot be enabled simultaneously.
      This patches adds an exclusive gate clock type specifically for such
      case.  The clock driver will need to call imx_clk_gate_exclusive() to
      register a gate clock with parameter exclusive_mask indicating the mask
      of gate bits which are mutually exclusive to this gate clock.
      
      Right now, it only handles the exclusive gate clocks which are defined
      in a single hardware register, which is the case we're running into
      today.  But it can be extended to handle exclusive gate clocks defined
      in different registers later if needed.
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      19d86344
  9. 18 Jul, 2014 2 commits
  10. 12 May, 2014 1 commit
    • Shawn Guo's avatar
      ARM: imx: add shared gate clock support · f9f28cdf
      Shawn Guo authored
      It's quite common on i.MX that one gate bit controls the gating of
      multiple clocks, i.e. this is a shared gate.  The patch adds the
      function imx_clk_gate2_shared() for such case.  The clocks controlled
      by the same gate bits should call this function with a pointer to a
      single share count variable, so that the gate bits will only be
      operated on the first enabling and the last disabling of these shared
      gate clocks.
      
      Thanks to Gerhard Sittig <gsi@denx.de> for this idea.
      Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
      f9f28cdf
  11. 19 Aug, 2013 1 commit
    • James Hogan's avatar
      clk: add CLK_SET_RATE_NO_REPARENT flag · 819c1de3
      James Hogan authored
      Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
      being reparented during clk_set_rate.
      
      To avoid breaking existing platforms, all callers of clk_register_mux()
      are adjusted to pass the new flag. Platform maintainers are encouraged
      to remove the flag if they wish to allow mux reparenting on set_rate.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Viresh Kumar <viresh.linux@gmail.com>
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
      Cc: Chao Xie <xiechao.mail@gmail.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: "Emilio López" <emilio@elopez.com.ar>
      Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Andrew Chew <achew@nvidia.com>
      Cc: Doug Anderson <dianders@chromium.org>
      Cc: Heiko Stuebner <heiko@sntech.de>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
      Cc: Thomas Abraham <thomas.abraham@linaro.org>
      Cc: Tomasz Figa <t.figa@samsung.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-samsung-soc@vger.kernel.org
      Cc: spear-devel@list.st.com
      Cc: linux-tegra@vger.kernel.org
      Tested-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
      Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
      Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
      Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      819c1de3
  12. 15 Aug, 2013 3 commits
    • Liu Ying's avatar
      ARM: imx6: change some clocks to fixup clocks · dfd87144
      Liu Ying authored
      All the clocks controlled by the register 'CCM Serial Clock
      Multiplexer Register 1' should be fixup clocks. This patch
      changes those clocks from basic multiplexer or divider clocks
      to fixup clocks.
      Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      dfd87144
    • Liu Ying's avatar
      ARM: imx: add common clock support for fixup mux · a49e6c4b
      Liu Ying authored
      One register may have several fields to control some clocks. It
      is possible that the read/write values of some fields may map to
      different real functional values, so writing to the other fields
      in the same register may break a working clock tree. A real case
      is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
      Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
      for multiplexer clock which is called before writing a value to
      clock registers to support this kind of multiplexer clocks.
      Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      a49e6c4b
    • Liu Ying's avatar
      ARM: imx: add common clock support for fixup div · cbe7fc8a
      Liu Ying authored
      One register may have several fields to control some clocks. It
      is possible that the read/write values of some fields may map to
      different real functional values, so writing to the other fields
      in the same register may break a working clock tree. A real case
      is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
      Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
      for divider clock which is called before writing a value to clock
      registers to support this kind of divider clocks.
      Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      cbe7fc8a
  13. 17 Jun, 2013 2 commits
    • Jiada Wang's avatar
      ARM: imx: remove MLB PLL from pllv3 · 71ed5477
      Jiada Wang authored
      MLB PLL should be handled internally in MLB driver,
      so remove it from pllv3.
      Signed-off-by: default avatarJiada Wang <jiada_wang@mentor.com>
      CC: Dirk Behme <dirk.behme@de.bosch.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      71ed5477
    • Martin Fuzzey's avatar
      ARM: i.MX5: Allow DT clock providers · 75f83d06
      Martin Fuzzey authored
      Currently clock providers defined in the DT are not registered
      on i.MX5 platforms since of_clk_init() is not called.
      
      This is not a problem for the SOC's own clocks, which are registered
      in code,  but prevents the DT being used to define clocks for external
      hardware.
      
      Fix this by calling of_clk_init() and actually using the DT to obtain
      the 4 SOC fixed clocks.
      These are already defined in the DT but were previously just used to
      manually obtain the rate.
      
      Fall back to the old scheme for non DT platforms.
      
      Since the same method may be useful for other i.MX platforms
      implement the imx_obtain_fixed_clock() function in common code.
      
      Actually changing other i.MX platforms to use this should be done
      later by someone with access to the appropriate hardware.
      Signed-off-by: default avatarMartin Fuzzey <mfuzzey@parkeon.com>
      Tested-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      75f83d06
  14. 12 Apr, 2013 1 commit
  15. 22 Nov, 2012 1 commit
  16. 12 Sep, 2012 1 commit
  17. 02 May, 2012 6 commits
  18. 25 Apr, 2012 1 commit