1. 06 Jun, 2012 2 commits
  2. 25 May, 2012 1 commit
    • Ben Widawsky's avatar
      drm/i915: wait render timeout ioctl · 23ba4fd0
      Ben Widawsky authored
      This helps implement GL_ARB_sync but stops short of allowing full blown
      sync objects. Finally we can use the new timed seqno waiting function
      to allow userspace to wait on a buffer object with a timeout. This
      implements that interface.
      The IOCTL will take as input a buffer object handle, and a timeout in
      nanoseconds (flags is currently optional but will likely be used for
      permutations of flush operations). Users may specify 0 nanoseconds to
      instantly check.
      The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
      non-zero timeout parameter the wait ioctl will wait for the given number
      of nanoseconds on an object becoming unbusy. Since the wait itself does
      so holding struct_mutex the object may become re-busied before this
      completes. A similar but shorter race condition exists in the busy
      v2: ETIME/ERESTARTSYS instead of changing to EBUSY, and EGAIN (Chris)
      Flush the object from the gpu write domain (Chris + Daniel)
      Fix leaked refcount in good case (Chris)
      Naturally align ioctl struct (Chris)
      v3: Drop lock after getting seqno to avoid ugly dance (Chris)
      v4: check for 0 timeout after olr check to allow polling (Chris)
      v5: Updated the comment. (Chris)
      v6: Return -ETIME instead of -EBUSY when timeout_ns is 0 (Daniel)
      Fix the commit message comment to be less ugly (Ben)
      Add a warning to check the return timespec (Ben)
      v7: Use DRM_AUTH for the ioctl. (Eugeni)
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
  3. 20 Mar, 2012 1 commit
    • Daniel Vetter's avatar
      drm/i915: add HAS_ALIASING_PPGTT parameter for userspace · 777ee96f
      Daniel Vetter authored
      On Sanybridge a few MI read/write commands only work when ppgtt is
      enabled.  Userspace therefore needs to be able to check whether ppgtt
      is enabled. For added hilarity, you need to reset the "use global GTT"
      bit on snb when ppgtt is enabled, otherwise it won't work.  Despite
      what bspec says about automatically using ppgtt ...
      Luckily PIPE_CONTROL (the only write cmd current userspace uses) is
      not affected by all this, as tested by tests/gem_pipe_control_store_loop.
      Reviewed-and-tested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
  4. 17 Jan, 2012 1 commit
  5. 03 Jan, 2012 2 commits
    • Eric Anholt's avatar
      drm/i915: Add support for resetting the SO write pointers on gen7. · ae662d31
      Eric Anholt authored
      These registers are automatically incremented by the hardware during
      transform feedback to track where the next streamed vertex output
      should go.  Unlike the previous generation, which had a packet for
      setting the corresponding registers to a defined value, gen7 only has
      MI_LOAD_REGISTER_IMM to do so.  That's a secure packet (since it loads
      an arbitrary register), so we need to do it from the kernel, and it
      needs to be settable atomically with the batchbuffer execution so that
      two clients doing transform feedback don't stomp on each others'
      Instead of building a more complicated interface involcing setting the
      registers to a specific value, just set them to 0 when asked and
      userland can tweak its pointers accordingly.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
      Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
    • Jesse Barnes's avatar
      drm/i915: add color key support v4 · 8ea30864
      Jesse Barnes authored
      Add new ioctls for getting and setting the current destination color
      key.  This allows for simple overlay display control by matching a color
      key value in the primary plane before blending the overlay on top.
      v2: remove unnecessary mutex acquire/release around reg accesses
      v3: add support for full color key management
      v4: fix copy & paste bug in snb_get_colorkey
          don't bother checking min/max values against docs as the docs are likely
          wrong (how could we handle 10bpc surface formats?)
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
  6. 22 Jul, 2011 1 commit
  7. 01 Mar, 2011 1 commit
  8. 20 Dec, 2010 1 commit
  9. 05 Dec, 2010 1 commit
  10. 29 Oct, 2010 1 commit
    • Chris Wilson's avatar
      drm/i915: Only enforce fence limits inside the GTT. · a00b10c3
      Chris Wilson authored
      So long as we adhere to the fence registers rules for alignment and no
      overlaps (including with unfenced accesses to linear memory) and account
      for the tiled access in our size allocation, we do not have to allocate
      the full fenced region for the object. This allows us to fight the bloat
      tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside
      the GTT we still suffer the additional alignment constraints, so it doesn't
      magic allow us to render larger scenes without stalls -- we need the
      expanded GTT and fence pipelining to overcome those...]
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
  11. 21 Oct, 2010 1 commit
  12. 16 Aug, 2010 1 commit
    • Dave Airlie's avatar
      drm: block userspace under allocating buffer and having drivers overwrite it (v2) · 1b2f1489
      Dave Airlie authored
      With the current screwed but its ABI, ioctls for the drm, Linus pointed out that we could allow userspace to specify the allocation size, but we pass it to the driver which then uses it blindly to store a struct. Now if userspace specifies the allocation size as smaller than the driver needs, the driver can possibly overwrite memory.
      This patch restructures the driver ioctls so we store the structure size we are expecting, and make sure we allocate at least that size. The copy from/to userspace are still restricted to the size the user specifies, this allows ioctl structs to grow on both sides of the equation.
      Up until now we didn't really use the DRM_IOCTL defines in the kernel, so this cleans them up and adds them for nouveau.
      fix nouveau pushbuf arg (thanks to Ben for pointing it out)
      Reported-by: default avatarLinus Torvalds <torvalds@linuxfoundation.org>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  13. 03 Aug, 2010 1 commit
    • Jesse Barnes's avatar
      x86 platform driver: intelligent power sharing driver · aa7ffc01
      Jesse Barnes authored
      Intel Core i3/5 platforms with integrated graphics support both CPU and
      GPU turbo mode.  CPU turbo mode is opportunistic: the CPU will use any
      available power to increase core frequencies if thermal headroom is
      available.  The GPU side is more manual however; the graphics driver
      must monitor GPU power and temperature and coordinate with a core
      thermal driver to take advantage of available thermal and power headroom
      in the package.
      The intelligent power sharing (IPS) driver is intended to coordinate
      this activity by monitoring MCP (multi-chip package) temperature and
      power, allowing the CPU and/or GPU to increase their power consumption,
      and thus performance, when possible.  The goal is to maximize
      performance within a given platform's TDP (thermal design point).
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarMatthew Garrett <mjg@redhat.com>
  14. 01 Jun, 2010 1 commit
  15. 26 May, 2010 1 commit
  16. 06 Jan, 2010 1 commit
  17. 03 Dec, 2009 1 commit
  18. 01 Dec, 2009 2 commits
  19. 05 Nov, 2009 1 commit
    • Daniel Vetter's avatar
      drm/i915: implement drmmode overlay support v4 · 02e792fb
      Daniel Vetter authored
      This implements intel overlay support for kms via a device-specific
      ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on
      dri-devel). We've reached the conclusion that such an infrastructure
      only makes sense when multiple kms overlay implementations exists,
      which atm don't (and it doesn't look like this is gonna change).
      Open issues:
      - Runs in sync with the gpu, i.e. unnecessary waiting. I've decided
        to wait on this because the hw tends to hang when changing something
        in this area. I left some dummy functions as infrastructure.
      - polyphase filtering uses a static table.
      - uses uninterruptible sleeps. Unfortunately the alternatives may
        unnecessarily wedged the hw if/when we timeout too early (and
        userspace only overloaded the batch buffers with stuff worth a few
        secs of gpu time).
      Changes since v1:
      - fix off-by-one misconception on my side. This fixes fullscreen
      Changes since v2:
      - add underrun detection as spec'ed for i965.
      - flush caches properly, fixing visual corruptions.
      Changes since v4:
      - fix up cache flushing of overlay memory regs.
      - killed require_pipe_a logic - it hangs the chip.
      Tested-By: diego.abelenda@gmail.com (on a 865G)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      [anholt: Resolved against the MADVISE ioctl going in before this one]
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
  20. 22 Sep, 2009 1 commit
  21. 17 Sep, 2009 1 commit
  22. 14 May, 2009 1 commit
  23. 08 Apr, 2009 1 commit
    • Eric Anholt's avatar
      drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU. · 280b713b
      Eric Anholt authored
      Save the bit 17 state of the pages when freeing the page list, and
      reswizzle them if necessary when rebinding the pages (in case they were
      swapped out).  Since we have userland with expectations that the swizzle
      enums let it pread and pwrite contents accurately, we can't expose a new
      swizzle enum for bit 17 (which it would have to GTT map to handle), so we
      handle it down in pread and pwrite by swizzling the copy when bit 17 of the
      page address is set.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
  24. 26 Mar, 2009 1 commit
  25. 08 Feb, 2009 1 commit
  26. 29 Dec, 2008 4 commits
  27. 02 Nov, 2008 1 commit
  28. 17 Oct, 2008 2 commits
  29. 13 Jul, 2008 1 commit
    • Dave Airlie's avatar
      drm: reorganise drm tree to be more future proof. · c0e09200
      Dave Airlie authored
      With the coming of kernel based modesetting and the memory manager stuff,
      the everything in one directory approach was getting very ugly and
      starting to be unmanageable.
      This restructures the drm along the lines of other kernel components.
      It creates a drivers/gpu/drm directory and moves the hw drivers into
      subdirectores. It moves the includes into an include/drm, and
      sets up the unifdef for the userspace headers we should be exporting.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  30. 06 May, 2008 1 commit
  31. 26 Apr, 2008 1 commit
    • Jesse Barnes's avatar
      drm/vbl rework: rework how the drm deals with vblank. · ac741ab7
      Jesse Barnes authored
      Other Authors: Michel Dänzer <michel@tungstengraphics.com>
      mga: Ian Romanick <idr@us.ibm.com>
      via: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
      This re-works the DRM internals to provide a better interface for drivers
      to expose vblank on multiple crtcs.
      It also includes work done by Michel on making i915 triple buffering and pageflipping work properly.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  32. 10 Jul, 2007 1 commit
  33. 09 Jun, 2007 1 commit