1. 29 Aug, 2012 3 commits
  2. 20 Aug, 2012 2 commits
  3. 13 Aug, 2012 2 commits
  4. 08 Aug, 2012 1 commit
  5. 16 Jun, 2012 1 commit
  6. 09 May, 2012 1 commit
  7. 26 Mar, 2012 1 commit
  8. 20 Mar, 2012 3 commits
  9. 29 Feb, 2012 1 commit
  10. 13 Feb, 2012 2 commits
    • Jerome Glisse's avatar
      drm/radeon: add support for evergreen/ni tiling informations v11 · 285484e2
      Jerome Glisse authored
      
      
      evergreen and northern island gpu needs more informations for 2D tiling
      than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace
      to provide those.
      
      The v8 cs checking change to track color view on r6xx/r7xx doesn't
      affect old userspace as old userspace always emited 0 for this register.
      
      v2 fix r6xx/r7xx 2D tiling computation
      v3 fix r6xx/r7xx height align for untiled surface & add support for
         tile split on evergreen and newer
      v4 improve tiling debugging output
      v5 fix tile split code for evergreen and newer
      v6 set proper tile split for crtc register
      v7 fix tile split limit value
      v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs
         checking, update safe reg for r600, evergreen and cayman.
         Evergreen checking need some work around for stencil alignment
         issues
      v9 fix tile split value range, fix compressed texture handling and
         mipmap calculation, allow evergreen check to be silencious in
         front of current broken userspace (depth/stencil alignment issue)
      v10 fix eg 3d texture and compressed texture, fix r600 depth array,
          fix r600 color view computation, add support for evergreen stencil
          split
      v11 more verbose debugging in some case
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      285484e2
    • Marek Olšák's avatar
      drm/radeon/kms: add support for streamout v7 · dd220a00
      Marek Olšák authored
      
      
      v2: agd5f: add strmout CS checking, copy_dw register checking
      
      v3: agd5f: don't use cs_check_reg() for copy_dw checking as it
      will incorrectly patch the command stream for certain regs.
      
      v4: agd5f: add warning if safe reg check fails for copy_dw
      
      v5: agd5f: add stricter checking for 6xx/7xx
      
      v6: agd5f: add range checking for copy_dw on eg+,
      add sx_surface_sync to safe reg list for 7xx.
      
      v7: agd5f: add stricter checking for eg+
      Signed-off-by: default avatarMarek Olšák <maraeo@gmail.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      dd220a00
  11. 06 Jan, 2012 1 commit
    • Jerome Glisse's avatar
      drm/radeon: GPU virtual memory support v22 · 721604a1
      Jerome Glisse authored
      
      
      Virtual address space are per drm client (opener of /dev/drm).
      Client are in charge of virtual address space, they need to
      map bo into it by calling DRM_RADEON_GEM_VA ioctl.
      
      First 16M of virtual address space is reserved by the kernel.
      
      Once using 2 level page table we should be able to have a small
      vram memory footprint for each pt (there would be one pt for all
      gart, one for all vram and then one first level for each virtual
      address space).
      
      Plan include using the sub allocator for a common vm page table
      area and using memcpy to copy vm page table in & out. Or use
      a gart object and copy things in & out using dma.
      
      v2: agd5f fixes:
      - Add vram base offset for vram pages.  The GPU physical address of a
      vram page is FB_OFFSET + page offset.  FB_OFFSET is 0 on discrete
      cards and the physical bus address of the stolen memory on
      integrated chips.
      - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
      
      v3: agd5f:
      - integrate with the semaphore/multi-ring stuff
      
      v4:
      - rebase on top ttm dma & multi-ring stuff
      - userspace is now in charge of the address space
      - no more specific cs vm ioctl, instead cs ioctl has a new
        chunk
      
      v5:
      - properly handle mem == NULL case from move_notify callback
      - fix the vm cleanup path
      
      v6:
      - fix update of page table to only happen on valid mem placement
      
      v7:
      - add tlb flush for each vm context
      - add flags to define mapping property (readable, writeable, snooped)
      - make ring id implicit from ib->fence->ring, up to each asic callback
        to then do ring specific scheduling if vm ib scheduling function
      
      v8:
      - add query for ib limit and kernel reserved virtual space
      - rename vm->size to max_pfn (maximum number of page)
      - update gem_va ioctl to also allow unmap operation
      - bump kernel version to allow userspace to query for vm support
      
      v9:
      - rebuild page table only when bind and incrementaly depending
        on bo referenced by cs and that have been moved
      - allow virtual address space to grow
      - use sa allocator for vram page table
      - return invalid when querying vm limit on non cayman GPU
      - dump vm fault register on lockup
      
      v10: agd5f:
      - Move the vm schedule_ib callback to a standalone function, remove
        the callback and use the existing ib_execute callback for VM IBs.
      
      v11:
      - rebase on top of lastest Linus
      
      v12: agd5f:
      - remove spurious backslash
      - set IB vm_id to 0 in radeon_ib_get()
      
      v13: agd5f:
      - fix handling of RADEON_CHUNK_ID_FLAGS
      
      v14:
      - fix va destruction
      - fix suspend resume
      - forbid bo to have several different va in same vm
      
      v15:
      - rebase
      
      v16:
      - cleanup left over of vm init/fini
      
      v17: agd5f:
      - cs checker
      
      v18: agd5f:
      - reworks the CS ioctl to better support multiple rings and
      VM.  Rather than adding a new chunk id for VM, just re-use the
      IB chunk id and add a new flags for VM mode.  Also define additional
      dwords for the flags chunk id to define the what ring we want to use
      (gfx, compute, uvd, etc.) and the priority.
      
      v19:
      - fix cs fini in weird case of no ib
      - semi working flush fix for ni
      - rebase on top of sa allocator changes
      
      v20: agd5f:
      - further CS ioctl cleanups from Christian's comments
      
      v21: agd5f:
      - integrate CS checker improvements
      
      v22: agd5f:
      - final cleanups for release, only allow VM CS on cayman
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      721604a1
  12. 20 Nov, 2011 1 commit
    • Marek Olšák's avatar
      drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS · e70f224c
      Marek Olšák authored
      
      
      This adds a new optional chunk to the CS ioctl that specifies optional flags
      to the CS parser. Why this is useful is explained below. Note that some regs
      no longer need the NOP relocation packet if this feature is enabled.
      Tested on r300g and r600g with this flag disabled and enabled.
      
      Assume there are two contexts sharing the same mipmapped tiled texture.
      One context wants to render into the first mipmap and the other one
      wants to render into the last mipmap. As you probably know, the hardware
      has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps,
      but that only applies to samplers.
      (at least on r300-r500, though later hardware likely behaves the same)
      
      So we want to just re-set the tiling flags before rendering (writing
      packets), right? ... No. The contexts run in parallel, so they may
      set the tiling flags simultaneously and then fire their command streams
      also simultaneously. The last one setting the flags wins, the other one
      loses.
      
      Another problem is when one context wants to render into the first and
      the last mipmap in one CS. Impossible. It must flush before changing
      tiling flags and do the rendering into the smaller mipmaps in another CS.
      
      Yet another problem is that writing copy_blit in userspace would be a mess
      involving re-setting tiling flags to please the kernel, and causing races
      with other contexts at the same time.
      
      The only way out of this is to send tiling flags with each CS, ideally
      with each relocation. But we already do that through the registers.
      So let's just use what we have in the registers.
      Signed-off-by: default avatarMarek Olšák <maraeo@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      e70f224c
  13. 18 Oct, 2011 2 commits
  14. 04 Aug, 2011 1 commit
  15. 20 Jun, 2011 1 commit
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  20. 27 Feb, 2011 2 commits
  21. 22 Feb, 2011 1 commit
  22. 13 Feb, 2011 1 commit
  23. 15 Dec, 2010 1 commit
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  26. 14 Nov, 2010 1 commit
  27. 27 Oct, 2010 1 commit
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  29. 25 Oct, 2010 2 commits