1. 10 Jul, 2013 1 commit
  2. 02 Jul, 2013 3 commits
  3. 25 Jun, 2013 2 commits
  4. 24 Jun, 2013 5 commits
  5. 19 Jun, 2013 6 commits
  6. 17 Jun, 2013 1 commit
    • Michael Chan's avatar
      tg3: Prevent system hang during repeated EEH errors. · 72bb72b0
      Michael Chan authored
      The current tg3 code assumes the pci_error_handlers to be always called
      in sequence.  In particular, during ->error_detected(), NAPI is disabled
      and the device is shutdown.  The device is later reset and NAPI
      re-enabled in ->slot_reset() and ->resume().
      In EEH, if more than 6 errors are detected in a hour, only
      ->error_detected() will be called.  This will leave the driver in an
      inconsistent state as NAPI is disabled but netif_running state is still
      true.  When the device is later closed, we'll try to disable NAPI again
      and it will loop forever.
      We fix this by closing the device if we encounter any error conditions
      during the normal sequence of the pci_error_handlers.
      v2: Remove the changes in tg3_io_resume() based on Benjamin Poirier's
      Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
      Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
  7. 13 Jun, 2013 2 commits
    • Florian Fainelli's avatar
      bcm63xx_enet: add support Broadcom BCM6345 Ethernet · 3dc6475c
      Florian Fainelli authored
      This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
      has a slightly different and older DMA engine which requires the
      following modifications:
      - the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
        which means that the helpers enet_dma{c,s} need to account for this
        channel width and we can no longer use macros
      - BCM6345 DMA engine does not have any internal SRAM for transfering
      - BCM6345 buffer allocation and flow control is not per-channel but
        global (done in RSET_ENETDMA)
      - the DMA engine bits are right-shifted by 3 compared to other DMA
      - the DMA enable/interrupt masks are a little different (we need to
        enabled more bits for 6345)
      - some register have the same meaning but are offsetted in the ENET_DMAC
        space so a lookup table is required to return the proper offset
      The MAC itself is identical and requires no modifications to work.
      Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    • Nithin Sujir's avatar
      tg3: Wait for boot code to finish after power on · df465abf
      Nithin Sujir authored
      Some systems that don't need wake-on-lan may choose to power down the
      chip on system standby. Upon resume, the power on causes the boot code
      to startup and initialize the hardware. On one new platform, this is
      causing the device to go into a bad state due to a race between the
      driver and boot code, once every several hundred resumes. The same race
      exists on open since we come up from a power on.
      This patch adds a wait for boot code signature at the beginning of
      tg3_init_hw() which is common to both cases. If there has not been a
      power-off or the boot code has already completed, the signature will be
      present and poll_fw() returns immediately. Also return immediately if
      the device does not have firmware.
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
      Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
  8. 10 Jun, 2013 3 commits
  9. 04 Jun, 2013 3 commits
  10. 03 Jun, 2013 1 commit
  11. 02 Jun, 2013 6 commits
  12. 01 Jun, 2013 1 commit
  13. 28 May, 2013 1 commit
  14. 27 May, 2013 5 commits