1. 23 Jan, 2015 7 commits
  2. 22 Jan, 2015 3 commits
  3. 16 Jan, 2015 2 commits
  4. 15 Jan, 2015 9 commits
    • Kevin Hao's avatar
      arm64: kill off the libgcc dependency · d67703a8
      Kevin Hao authored
      The arm64 kernel builds fine without the libgcc. Actually it should not
      be used at all in the kernel. The following are the reasons indicated
      by Russell King:
      
        Although libgcc is part of the compiler, libgcc is built with the
        expectation that it will be running in userland - it expects to link
        to a libc.  That's why you can't build libgcc without having the glibc
        headers around.
      
        [...]
      
        Meanwhile, having the kernel build the compiler support functions that
        it needs ensures that (a) we know what compiler support functions are
        being used, (b) we know the implementation of those support functions
        are sane for use in the kernel, (c) we can build them with appropriate
        compiler flags for best performance, and (d) we remove an unnecessary
        dependency on the build toolchain.
      Signed-off-by: default avatarKevin Hao <haokexin@gmail.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      d67703a8
    • Mark Rutland's avatar
      arm64: kvm: decode ESR_ELx.EC when reporting exceptions · 056bb5f5
      Mark Rutland authored
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value using the
      newly introduced esr_get_class_string. This doesn't tell the developer
      the specifics of the exception encoded in the remaining IL and ISS bits,
      but it can be helpful to distinguish between exception classes (e.g.
      SError and a data abort) without having to manually decode the field,
      which can be tiresome.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      056bb5f5
    • Mark Rutland's avatar
      arm64: kvm: remove ESR_EL2_* macros · 6e53031e
      Mark Rutland authored
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL2 macros. To maintain compatibility with the
      fault handling code shared with 32-bit, the FSC_{FAULT,PERM} macros are
      retained as aliases for the common ESR_ELx_FSC_{FAULT,PERM} definitions.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      6e53031e
    • Mark Rutland's avatar
      arm64: remove ESR_EL1_* macros · 4a939087
      Mark Rutland authored
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL1 macros.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      4a939087
    • Mark Rutland's avatar
      arm64: kvm: move to ESR_ELx macros · c6d01a94
      Mark Rutland authored
      Now that we have common ESR_ELx macros, make use of them in the arm64
      KVM code. The addition of <asm/esr.h> to the include path highlighted
      badly ordered (i.e. not alphabetical) include lists; these are changed
      to alphabetical order.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      c6d01a94
    • Mark Rutland's avatar
      arm64: decode ESR_ELx.EC when reporting exceptions · 60a1f02c
      Mark Rutland authored
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value. This doesn't
      tell the developer the specifics of the exception encoded in the
      remaining IL and ISS bits, but it can be helpful to distinguish between
      exception classes (e.g. SError and a data abort) without having to
      manually decode the field, which can be tiresome.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      60a1f02c
    • Mark Rutland's avatar
      arm64: move to ESR_ELx macros · aed40e01
      Mark Rutland authored
      Now that we have common ESR_ELx_* macros, move the core arm64 code over
      to them.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      aed40e01
    • Mark Rutland's avatar
      arm64: introduce common ESR_ELx_* definitions · cf99a48d
      Mark Rutland authored
      Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
      the encodings are common. While encodings are architected to refer to
      the current EL or a lower EL, the macros refer to particular ELs (e.g.
      ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
      and their naming is misleading.
      
      This patch introduces common ESR_ELx_* macros that can be used in all
      cases, in preparation for later patches which will migrate existing
      users over. Some additional cleanups are made in the process:
      
      * Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
        replaced with more general _LOW and _CUR suffixes, matching the
        architectural intent.
      
      * ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
        EC encoding covers traps from both WFE and WFI. Similarly,
        ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
      
      * Multi-bit fields are given consistently named _SHIFT and _MASK macros.
      
      * UL() is used for compatiblity with assembly files.
      
      * Comments are added for currently unallocated ESR_ELx.EC encodings.
      
      For fields other than ESR_ELx.EC, macros are only implemented for fields
      for which there is already an ESR_EL{1,2}_* macro.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      cf99a48d
    • Sudeep Holla's avatar
      arm64: kernel: add support for cpu cache information · 5d425c18
      Sudeep Holla authored
      This patch adds support for cacheinfo on ARM64.
      
      On ARMv8, the cache hierarchy can be identified through Cache Level ID
      (CLIDR) register while the cache geometry is provided by Cache Size ID
      (CCSIDR) register.
      
      Since the architecture doesn't provide any way of detecting the cpus
      sharing particular cache, device tree is used for the same purpose.
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      5d425c18
  5. 13 Jan, 2015 1 commit
    • Mark Rutland's avatar
      arm64: remove broken cachepolicy code · 26a945ca
      Mark Rutland authored
      The cachepolicy kernel parameter was intended to aid in the debugging of
      coherency issues, but it is fundamentally broken for several reasons:
      
       * On SMP platforms, only the boot CPU's tcr_el1 is altered. Secondary
         CPUs may therefore use differ w.r.t. the attributes they apply to
         MT_NORMAL memory, resulting in a loss of coherency.
      
       * The cache maintenance using flush_dcache_all (based on Set/Way
         operations) is not guaranteed to empty a given CPU's cache hierarchy
         while said CPU has caches enabled, it cannot empty the caches of
         other coherent PEs, nor is it guaranteed to flush data to the PoC
         even when caches are disabled.
      
       * The TLBs are not invalidated around the modification of MAIR_EL1 and
         TCR_EL1, as required by the architecture (as both are permitted to be
         cached in a TLB). This may result in CPUs using attributes other than
         those expected for some memory accesses, resulting in a loss of
         coherency.
      
       * Exclusive accesses are not architecturally guaranteed to function as
         expected on memory marked as Write-Through or Non-Cacheable. Thus
         changing the attributes of MT_NORMAL away from the (architecurally
         safe) defaults may cause uses of these instructions (e.g. atomics) to
         behave erratically.
      
      Given this, the cachepolicy code cannot be used for debugging purposes
      as it alone is likely to cause coherency issues. This patch removes the
      broken cachepolicy code.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      26a945ca
  6. 12 Jan, 2015 6 commits
  7. 09 Jan, 2015 1 commit
  8. 08 Jan, 2015 1 commit
    • Ard Biesheuvel's avatar
      arm64/efi: add missing call to early_ioremap_reset() · 0e63ea48
      Ard Biesheuvel authored
      The early ioremap support introduced by patch bf4b558e
      ("arm64: add early_ioremap support") failed to add a call to
      early_ioremap_reset() at an appropriate time. Without this call,
      invocations of early_ioremap etc. that are done too late will go
      unnoticed and may cause corruption.
      
      This is exactly what happened when the first user of this feature
      was added in patch f84d0275 ("arm64: add EFI runtime services").
      The early mapping of the EFI memory map is unmapped during an early
      initcall, at which time the early ioremap support is long gone.
      
      Fix by adding the missing call to early_ioremap_reset() to
      setup_arch(), and move the offending early_memunmap() to right after
      the point where the early mapping of the EFI memory map is last used.
      
      Fixes: f84d0275 ("arm64: add EFI runtime services")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarLeif Lindholm <leif.lindholm@linaro.org>
      Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      0e63ea48
  9. 07 Jan, 2015 7 commits
  10. 23 Dec, 2014 3 commits
    • Jungseok Lee's avatar
      arm64: mm: Add pgd_page to support RCU fast_gup · 5d96e0cb
      Jungseok Lee authored
      This patch adds pgd_page definition in order to keep supporting
      HAVE_GENERIC_RCU_GUP configuration. In addition, it changes pud_page
      expression to align with pmd_page for readability.
      
      An introduction of pgd_page resolves the following build breakage
      under 4KB + 4Level memory management combo.
      
      mm/gup.c: In function 'gup_huge_pgd':
      mm/gup.c:889:2: error: implicit declaration of function 'pgd_page' [-Werror=implicit-function-declaration]
        head = pgd_page(orig);
        ^
      mm/gup.c:889:7: warning: assignment makes pointer from integer without a cast
        head = pgd_page(orig);
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Steve Capper <steve.capper@linaro.org>
      Signed-off-by: default avatarJungseok Lee <jungseoklee85@gmail.com>
      [catalin.marinas@arm.com: remove duplicate pmd_page definition]
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      5d96e0cb
    • Will Deacon's avatar
      arm64: defconfig: defconfig update for 3.19 · f7bf130e
      Will Deacon authored
      The usual defconfig tweaks, this time:
      
        - FHANDLE and AUTOFS4_FS to keep systemd happy
        - PID_NS, QUOTA and KEYS to keep LTP happy
        - Disable DEBUG_PREEMPT, as this *really* hurts performance
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      f7bf130e
    • Lorenzo Pieralisi's avatar
      arm64: kernel: fix __cpu_suspend mm switch on warm-boot · f43c2718
      Lorenzo Pieralisi authored
      On arm64 the TTBR0_EL1 register is set to either the reserved TTBR0
      page tables on boot or to the active_mm mappings belonging to user space
      processes, it must never be set to swapper_pg_dir page tables mappings.
      
      When a CPU is booted its active_mm is set to init_mm even though its
      TTBR0_EL1 points at the reserved TTBR0 page mappings. This implies
      that when __cpu_suspend is triggered the active_mm can point at
      init_mm even if the current TTBR0_EL1 register contains the reserved
      TTBR0_EL1 mappings.
      
      Therefore, the mm save and restore executed in __cpu_suspend might
      turn out to be erroneous in that, if the current->active_mm corresponds
      to init_mm, on resume from low power it ends up restoring in the
      TTBR0_EL1 the init_mm mappings that are global and can cause speculation
      of TLB entries which end up being propagated to user space.
      
      This patch fixes the issue by checking the active_mm pointer before
      restoring the TTBR0 mappings. If the current active_mm == &init_mm,
      the code sets the TTBR0_EL1 to the reserved TTBR0 mapping instead of
      switching back to the active_mm, which is the expected behaviour
      corresponding to the TTBR0_EL1 settings when __cpu_suspend was entered.
      
      Fixes: 95322526 ("arm64: kernel: cpu_{suspend/resume} implementation")
      Cc: <stable@vger.kernel.org> # 3.14+: 18ab7db6
      Cc: <stable@vger.kernel.org> # 3.14+: 714f5992
      Cc: <stable@vger.kernel.org> # 3.14+: c3684fbb
      Cc: <stable@vger.kernel.org> # 3.14+
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      f43c2718