1. 23 Jan, 2015 7 commits
  2. 22 Jan, 2015 3 commits
  3. 16 Jan, 2015 2 commits
  4. 15 Jan, 2015 9 commits
    • Kevin Hao's avatar
      arm64: kill off the libgcc dependency · d67703a8
      Kevin Hao authored
      The arm64 kernel builds fine without the libgcc. Actually it should not
      be used at all in the kernel. The following are the reasons indicated
      by Russell King:
      
        Although libgcc is part of the compiler, libgcc is built with the
        expectation that it will be running in userland - it expects to link
        to a libc.  That's why you can't build libgcc without having the glibc
        headers around.
      
        [...]
      
        Meanwhile, having the kernel build the compiler support functions that
        it needs ensures that (a) we know what compiler support functions are
        being used, (b) we know the implementation of those support functions
        are sane for use in the kernel, (c) we can build them with appropriate
        compiler flags for best performance, and (d) we remove an unnecessary
        dependency on the build toolchain.
      Signed-off-by: default avatarKevin Hao <haokexin@gmail.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      d67703a8
    • Mark Rutland's avatar
      arm64: kvm: decode ESR_ELx.EC when reporting exceptions · 056bb5f5
      Mark Rutland authored
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value using the
      newly introduced esr_get_class_string. This doesn't tell the developer
      the specifics of the exception encoded in the remaining IL and ISS bits,
      but it can be helpful to distinguish between exception classes (e.g.
      SError and a data abort) without having to manually decode the field,
      which can be tiresome.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      056bb5f5
    • Mark Rutland's avatar
      arm64: kvm: remove ESR_EL2_* macros · 6e53031e
      Mark Rutland authored
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL2 macros. To maintain compatibility with the
      fault handling code shared with 32-bit, the FSC_{FAULT,PERM} macros are
      retained as aliases for the common ESR_ELx_FSC_{FAULT,PERM} definitions.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      6e53031e
    • Mark Rutland's avatar
      arm64: remove ESR_EL1_* macros · 4a939087
      Mark Rutland authored
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL1 macros.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      4a939087
    • Mark Rutland's avatar
      arm64: kvm: move to ESR_ELx macros · c6d01a94
      Mark Rutland authored
      Now that we have common ESR_ELx macros, make use of them in the arm64
      KVM code. The addition of <asm/esr.h> to the include path highlighted
      badly ordered (i.e. not alphabetical) include lists; these are changed
      to alphabetical order.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      c6d01a94
    • Mark Rutland's avatar
      arm64: decode ESR_ELx.EC when reporting exceptions · 60a1f02c
      Mark Rutland authored
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value. This doesn't
      tell the developer the specifics of the exception encoded in the
      remaining IL and ISS bits, but it can be helpful to distinguish between
      exception classes (e.g. SError and a data abort) without having to
      manually decode the field, which can be tiresome.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      60a1f02c
    • Mark Rutland's avatar
      arm64: move to ESR_ELx macros · aed40e01
      Mark Rutland authored
      Now that we have common ESR_ELx_* macros, move the core arm64 code over
      to them.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      aed40e01
    • Mark Rutland's avatar
      arm64: introduce common ESR_ELx_* definitions · cf99a48d
      Mark Rutland authored
      Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
      the encodings are common. While encodings are architected to refer to
      the current EL or a lower EL, the macros refer to particular ELs (e.g.
      ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
      and their naming is misleading.
      
      This patch introduces common ESR_ELx_* macros that can be used in all
      cases, in preparation for later patches which will migrate existing
      users over. Some additional cleanups are made in the process:
      
      * Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
        replaced with more general _LOW and _CUR suffixes, matching the
        architectural intent.
      
      * ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
        EC encoding covers traps from both WFE and WFI. Similarly,
        ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
      
      * Multi-bit fields are given consistently named _SHIFT and _MASK macros.
      
      * UL() is used for compatiblity with assembly files.
      
      * Comments are added for currently unallocated ESR_ELx.EC encodings.
      
      For fields other than ESR_ELx.EC, macros are only implemented for fields
      for which there is already an ESR_EL{1,2}_* macro.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      cf99a48d
    • Sudeep Holla's avatar
      arm64: kernel: add support for cpu cache information · 5d425c18
      Sudeep Holla authored
      This patch adds support for cacheinfo on ARM64.
      
      On ARMv8, the cache hierarchy can be identified through Cache Level ID
      (CLIDR) register while the cache geometry is provided by Cache Size ID
      (CCSIDR) register.
      
      Since the architecture doesn't provide any way of detecting the cpus
      sharing particular cache, device tree is used for the same purpose.
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      5d425c18
  5. 13 Jan, 2015 1 commit
    • Mark Rutland's avatar
      arm64: remove broken cachepolicy code · 26a945ca
      Mark Rutland authored
      The cachepolicy kernel parameter was intended to aid in the debugging of
      coherency issues, but it is fundamentally broken for several reasons:
      
       * On SMP platforms, only the boot CPU's tcr_el1 is altered. Secondary
         CPUs may therefore use differ w.r.t. the attributes they apply to
         MT_NORMAL memory, resulting in a loss of coherency.
      
       * The cache maintenance using flush_dcache_all (based on Set/Way
         operations) is not guaranteed to empty a given CPU's cache hierarchy
         while said CPU has caches enabled, it cannot empty the caches of
         other coherent PEs, nor is it guaranteed to flush data to the PoC
         even when caches are disabled.
      
       * The TLBs are not invalidated around the modification of MAIR_EL1 and
         TCR_EL1, as required by the architecture (as both are permitted to be
         cached in a TLB). This may result in CPUs using attributes other than
         those expected for some memory accesses, resulting in a loss of
         coherency.
      
       * Exclusive accesses are not architecturally guaranteed to function as
         expected on memory marked as Write-Through or Non-Cacheable. Thus
         changing the attributes of MT_NORMAL away from the (architecurally
         safe) defaults may cause uses of these instructions (e.g. atomics) to
         behave erratically.
      
      Given this, the cachepolicy code cannot be used for debugging purposes
      as it alone is likely to cause coherency issues. This patch removes the
      broken cachepolicy code.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      26a945ca
  6. 12 Jan, 2015 6 commits
  7. 09 Jan, 2015 5 commits
  8. 08 Jan, 2015 2 commits
  9. 07 Jan, 2015 5 commits
    • Grygorii Strashko's avatar
      ARM: 8253/1: mm: use phys_addr_t type in map_lowmem() for kernel mem region · ac084688
      Grygorii Strashko authored
      Now local variables kernel_x_start and kernel_x_end defined using
      'unsigned long' type which is wrong because they represent physical
      memory range and will be calculated wrongly if LPAE is enabled.
      As result, all following code in map_lowmem() will not work correctly.
      
      For example, Keystone 2 boot is broken because
       kernel_x_start == 0x0000 0000
       kernel_x_end   == 0x0080 0000
      
      instead of
       kernel_x_start == 0x0000 0008 0000 0000
       kernel_x_end   == 0x0000 0008 0080 0000
      and as result whole low memory will be mapped with MT_MEMORY_RW
      permissions by code (start > kernel_x_end):
      		} else if (start >= kernel_x_end) {
      			map.pfn = __phys_to_pfn(start);
      			map.virtual = __phys_to_virt(start);
      			map.length = end - start;
      			map.type = MT_MEMORY_RW;
      
      			create_mapping(&map);
      		}
      
      Hence, fix it by using phys_addr_t type for variables kernel_x_start
      and kernel_x_end.
      Tested-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ac084688
    • Mark Rutland's avatar
      ARM: 8249/1: mm: dump: don't skip regions · cca547e9
      Mark Rutland authored
      Currently the arm page table dumping code starts dumping page tables
      from USER_PGTABLES_CEILING. This is unnecessary for skipping any entries
      related to userspace as the swapper_pg_dir does not contain such
      entries, and results in a couple of unfortuante side effects.
      
      Firstly, any kernel mappings which might exist below
      USER_PGTABLES_CEILING will not be accounted in the dump output. This
      masks any entries erroneously created below this address.
      
      Secondly, if the final page table entry walked is part of a valid
      mapping the page table dumping code will not log the region this entry
      is part of, as the final note_page call in walk_pgd will trigger an
      early return when 0 < USER_PGTABLES_CEILING. Luckily this isn't seen on
      contemporary systems as they typically don't have enough RAM to extend
      the linear mapping right to the end of the address space.
      
      Due to the way addr is constructed in the walk_* functions, it can never
      be less than USER_PGTABLES_CEILING when walking the page tables, so it
      is not necessary to avoid dereferencing invalid table addresses. The
      existing checks for st->current_prot and st->marker[1].start_address are
      sufficient to ensure we will not print and/or dereference garbage when
      trying to log information.
      
      This patch removes both problematic uses of USER_PGTABLES_CEILING from
      the arm page table dumping code, preventing both of these issues. We
      will now report any low mappings, and the final note_page call will not
      return early, ensuring all regions are logged.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Steve Capper <steve.capper@linaro.org>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      cca547e9
    • Russell King's avatar
      ARM: wire up execveat syscall · 841ee230
      Russell King authored
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      841ee230
    • Paul Walmsley's avatar
      arm64: fix missing asm/io.h include in kernel/smp_spin_table.c · 59c68329
      Paul Walmsley authored
      On next-20150105, defconfig compilation breaks with:
      
      arch/arm64/kernel/smp_spin_table.c:80:2: error: implicit declaration of function ‘ioremap_cache’ [-Werror=implicit-function-declaration]
      arch/arm64/kernel/smp_spin_table.c:92:2: error: implicit declaration of function ‘writeq_relaxed’ [-Werror=implicit-function-declaration]
      arch/arm64/kernel/smp_spin_table.c:101:2: error: implicit declaration of function ‘iounmap’ [-Werror=implicit-function-declaration]
      
      Fix by including asm/io.h, which contains definitions or prototypes
      for these macros or functions.
      
      This second version incorporates a comment from Mark Rutland
      <mark.rutland@arm.com> to keep the includes in alphabetical order
      by filename.
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      59c68329
    • Paul Walmsley's avatar
      arm64: fix missing asm/alternative.h include in kernel/module.c · 2c2b282d
      Paul Walmsley authored
      On next-20150105, defconfig compilation breaks with:
      
      arch/arm64/kernel/module.c:408:4: error: implicit declaration of function ‘apply_alternatives’ [-Werror=implicit-function-declaration]
      
      Fix by including asm/alternative.h, where the apply_alternatives()
      prototype is declared.
      
      This second version incorporates a comment from Mark Rutland
      <mark.rutland@arm.com> to keep the includes in alphabetical order
      by filename.
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      2c2b282d