Commit f91e2c3b authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King

ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7

The current implementation of the dcache_line_size macro reads the L1
cache size from the CCSIDR register. This, however, is not guaranteed to
be the smallest cache line in the cache hierarchy. The patch changes to
the macro to use the more architecturally correct CTR register.
Reported-by: default avatarKevin Sapp <>
Signed-off-by: default avatarCatalin Marinas <>
Signed-off-by: default avatarRussell King <>
parent 6313e3c2
......@@ -61,14 +61,14 @@
* cache_line_size - get the cache line size from the CSIDR register
* (available on ARMv7+). It assumes that the CSSR register was configured
* to access the L1 data cache CSIDR.
* dcache_line_size - get the minimum D-cache line size from the CTR register
* on ARMv7.
.macro dcache_line_size, reg, tmp
mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
and \tmp, \tmp, #7 @ cache line size encoding
mov \reg, #16 @ size offset
mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
lsr \tmp, \tmp, #16
and \tmp, \tmp, #0xf @ cache line size encoding
mov \reg, #4 @ bytes per word
mov \reg, \reg, lsl \tmp @ actual cache line size
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