Commit f6e2373a authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] MIPSsim: Move code away from the other MIPS Inc. BSP code.

It shares no code at all.  While at it also fix up the beginning bitrot.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 24e9d0b9
......@@ -251,6 +251,7 @@ config MIPS_SIM
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This option enables support for MIPS Technologies MIPSsim software
......
......@@ -327,7 +327,7 @@ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000
#
# MIPS SIM
#
core-$(CONFIG_MIPS_SIM) += arch/mips/mips-boards/sim/
core-$(CONFIG_MIPS_SIM) += arch/mips/mipssim/
cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim
load-$(CONFIG_MIPS_SIM) += 0x80100000
......
......@@ -138,15 +138,14 @@
EXPORT(stext) # used for profiling
EXPORT(_stext)
#ifdef CONFIG_MIPS_SIM
#ifndef CONFIG_MIPS_SIM
/*
* Give us a fighting chance of running if execution beings at the
* kernel load address. This is needed because this platform does
* not have a ELF loader yet.
*/
j kernel_entry
#endif
__INIT
#endif
NESTED(kernel_entry, 16, sp) # kernel entry point
......@@ -197,9 +196,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
j start_kernel
END(kernel_entry)
#ifdef CONFIG_QEMU
__INIT
#endif
#ifdef CONFIG_SMP
/*
......
......@@ -18,8 +18,8 @@
* written by Ralf Baechle
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <asm/io.h>
static inline unsigned int serial_in(int offset)
{
......
/*
* Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/mips-boards/simint.h>
#include <asm/irq_cpu.h>
static inline int clz(unsigned long x)
{
__asm__ (
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (x)
: "r" (x));
return x;
}
/*
* Version of ffs that only looks at bits 12..15.
*/
static inline unsigned int irq_ffs(unsigned int pending)
{
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
return -clz(pending) + 31 - CAUSEB_IP;
#else
unsigned int a0 = 7;
unsigned int t0;
t0 = s0 & 0xf000;
t0 = t0 < 1;
t0 = t0 << 2;
a0 = a0 - t0;
s0 = s0 << t0;
t0 = s0 & 0xc000;
t0 = t0 < 1;
t0 = t0 << 1;
a0 = a0 - t0;
s0 = s0 << t0;
t0 = s0 & 0x8000;
t0 = t0 < 1;
/* t0 = t0 << 2; */
a0 = a0 - t0;
/* s0 = s0 << t0; */
return a0;
#endif
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
int irq;
irq = irq_ffs(pending);
if (irq > 0)
do_IRQ(MIPSCPU_INT_BASE + irq);
else
spurious_interrupt();
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
}
......@@ -95,7 +95,7 @@ void __init prom_meminit(void)
size = p->size;
add_memory_region(base, size, type);
p++;
p++;
}
}
......
......@@ -19,18 +19,18 @@
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/serial.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/mips-boards/sim.h>
#include <asm/mips-boards/simint.h>
......@@ -62,7 +62,7 @@ void __init plat_mem_setup(void)
#endif
}
void prom_init(void)
void __init prom_init(void)
{
set_io_port_base(0xbfd00000);
......
......@@ -22,13 +22,13 @@
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/smtc_ipi.h>
#endif /* CONFIG_MIPS_MT_SMTC */
......@@ -73,11 +73,19 @@ void prom_init_secondary(void)
#endif /* CONFIG_MIPS_MT_SMTC */
}
void plat_smp_setup(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
if (read_c0_config3() & (1 << 2))
mipsmt_build_cpu_map(0);
#endif /* CONFIG_MIPS_MT_SMTC */
}
/*
* Platform SMP pre-initialization
*/
void prom_prepare_cpus(unsigned int max_cpus)
void plat_prepare_cpus(unsigned int max_cpus)
{
#ifdef CONFIG_MIPS_MT_SMTC
/*
......@@ -85,8 +93,8 @@ void prom_prepare_cpus(unsigned int max_cpus)
* but it may be multithreaded.
*/
if (read_c0_config3() & (1<<2)) {
mipsmt_prepare_cpus(max_cpus);
if (read_c0_config3() & (1 << 2)) {
mipsmt_prepare_cpus();
}
#endif /* CONFIG_MIPS_MT_SMTC */
}
......
......@@ -5,10 +5,10 @@
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/mipsregs.h>
#include <linux/smp.h>
#include <linux/timex.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/hardirq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
......@@ -16,7 +16,6 @@
#include <asm/irq.h>
#include <asm/mc146818-time.h>
#include <asm/msc01_ic.h>
#include <asm/smp.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
......@@ -37,8 +36,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
#ifndef CONFIG_MIPS_MT_SMTC
if (cpu == 0) {
timer_interrupt(irq, dev_id);
}
else {
} else {
/* Everyone else needs to reset the timer int here as
ll_local_timer_interrupt doesn't */
/*
......@@ -76,8 +74,10 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
irq_enable_hazard();
evpe(vpflags);
if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id);
else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
if (cpu_data[cpu].vpe_id == 0)
timer_interrupt(irq, dev_id);
else
write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
#endif /* CONFIG_MIPS_MT_SMTC */
......@@ -85,7 +85,8 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
/*
* every CPU should do profiling and process accounting
*/
local_timer_interrupt (irq, dev_id);
local_timer_interrupt (irq, dev_id);
return IRQ_HANDLED;
#else
return timer_interrupt (irq, dev_id);
......@@ -152,17 +153,15 @@ void __init sim_time_init(void)
local_irq_save(flags);
/* Set Data mode - binary. */
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
est_freq = estimate_cpu_frequency ();
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
(est_freq % 1000000) * 100 / 1000000);
cpu_khz = est_freq / 1000;
cpu_khz = est_freq / 1000;
local_irq_restore(flags);
}
......@@ -180,8 +179,7 @@ void __init plat_timer_setup(struct irqaction *irq)
if (cpu_has_veic) {
set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
}
else {
} else {
if (cpu_has_vint)
set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
......
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