Commit ec65cfce authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by David S. Miller

sh_eth: rename ARSTR register bit

The Renesas RZ/A1H manual names the software reset bit in the software reset
register (ARSTR) ARST which makes a bit more sense than the ARSTR_ARSTR name
used now  by the driver -- rename the latter to ARSTR_ARST.
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 97717edc
......@@ -482,7 +482,7 @@ static void sh_eth_chip_reset(struct net_device *ndev)
struct sh_eth_private *mdp = netdev_priv(ndev);
/* reset device */
sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
mdelay(1);
}
......@@ -540,7 +540,7 @@ static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
struct sh_eth_private *mdp = netdev_priv(ndev);
/* reset device */
sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
mdelay(1);
sh_eth_select_mii(ndev);
......@@ -735,7 +735,7 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev)
}
/* reset device */
iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
iowrite32(ARSTR_ARST, (void *)(SH_GIGA_ETH_BASE + 0x1800));
mdelay(1);
/* restore MAHR and MALR */
......
......@@ -394,7 +394,7 @@ enum RPADIR_BIT {
#define DEFAULT_FDR_INIT 0x00000707
/* ARSTR */
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
enum ARSTR_BIT { ARSTR_ARST = 0x00000001, };
/* TSU_FWEN0 */
enum TSU_FWEN0_BIT {
......
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