Commit e77c232c authored by Franck Bui-Huu's avatar Franck Bui-Huu Committed by Ralf Baechle

[MIPS] Compile __do_IRQ() when really needed

__do_IRQ() is needed only by irq handlers that can't use
default handlers defined in kernel/irq/chip.c.

For others platforms there's no need to compile this function
since it won't be used. For those platforms this patch defines
GENERIC_HARDIRQS_NO__DO_IRQ symbol which is used exactly for
this purpose.

Futhermore for platforms which do not use __do_IRQ(), end()
method which is part of the 'irq_chip' structure is not used.
This patch simply removes this method in this case.
Signed-off-by: default avatarFranck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1ccd1c1c
......@@ -242,6 +242,7 @@ config LASAT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config MIPS_ATLAS
bool "MIPS Atlas board"
......@@ -265,6 +266,7 @@ config MIPS_ATLAS
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This enables support for the MIPS Technologies Atlas evaluation
board.
......@@ -419,6 +421,7 @@ config MOMENCO_OCELOT_C
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
......@@ -569,6 +572,7 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
......@@ -835,6 +839,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default n
#
# Select some configuration options automatically based on user selections.
#
......@@ -996,6 +1004,7 @@ config SOC_PNX8550
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_HARDIRQS_NO__DO_IRQ
config SWAP_IO_SPACE
bool
......
......@@ -67,7 +67,6 @@ static struct irq_chip ioasic_irq_type = {
.mask = mask_ioasic_irq,
.mask_ack = ack_ioasic_irq,
.unmask = unmask_ioasic_irq,
.end = end_ioasic_irq,
};
......
......@@ -57,19 +57,12 @@ static void ack_kn02_irq(unsigned int irq)
iob();
}
static void end_kn02_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
unmask_kn02_irq(irq);
}
static struct irq_chip kn02_irq_type = {
.typename = "KN02-CSR",
.ack = ack_kn02_irq,
.mask = mask_kn02_irq,
.mask_ack = ack_kn02_irq,
.unmask = unmask_kn02_irq,
.end = end_kn02_irq,
};
......
......@@ -56,19 +56,12 @@ static void emma2rh_irq_disable(unsigned int irq)
ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
}
static void emma2rh_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
}
struct irq_chip emma2rh_irq_controller = {
.typename = "emma2rh_irq",
.ack = emma2rh_irq_disable,
.mask = emma2rh_irq_disable,
.mask_ack = emma2rh_irq_disable,
.unmask = emma2rh_irq_enable,
.end = emma2rh_irq_end,
};
void emma2rh_irq_init(u32 irq_base)
......
......@@ -48,19 +48,12 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
}
static void emma2rh_sw_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
}
struct irq_chip emma2rh_sw_irq_controller = {
.typename = "emma2rh_sw_irq",
.ack = emma2rh_sw_irq_disable,
.mask = emma2rh_sw_irq_disable,
.mask_ack = emma2rh_sw_irq_disable,
.unmask = emma2rh_sw_irq_enable,
.end = emma2rh_sw_irq_end,
};
void emma2rh_sw_irq_init(u32 irq_base)
......
......@@ -39,19 +39,12 @@ void disable_r4030_irq(unsigned int irq)
spin_unlock_irqrestore(&r4030_lock, flags);
}
static void end_r4030_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_r4030_irq(irq);
}
static struct irq_chip r4030_irq_type = {
.typename = "R4030",
.ack = disable_r4030_irq,
.mask = disable_r4030_irq,
.mask_ack = disable_r4030_irq,
.unmask = enable_r4030_irq,
.end = end_r4030_irq,
};
void __init init_r4030_ints(void)
......
......@@ -66,15 +66,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
}
}
/*
* End IRQ processing
*/
static void end_mv64340_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_mv64340_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the Marvell chip.
* It could be built in ethernet ports etc...
......@@ -106,7 +97,6 @@ struct irq_chip mv64340_irq_type = {
.mask = mask_mv64340_irq,
.mask_ack = mask_mv64340_irq,
.unmask = unmask_mv64340_irq,
.end = end_mv64340_irq,
};
void __init mv64340_irq_init(unsigned int base)
......
......@@ -29,19 +29,12 @@ static inline void mask_rm7k_irq(unsigned int irq)
clear_c0_intcontrol(0x100 << (irq - irq_base));
}
static void rm7k_cpu_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
unmask_rm7k_irq(irq);
}
static struct irq_chip rm7k_irq_controller = {
.typename = "RM7000",
.ack = mask_rm7k_irq,
.mask = mask_rm7k_irq,
.mask_ack = mask_rm7k_irq,
.unmask = unmask_rm7k_irq,
.end = rm7k_cpu_irq_end,
};
void __init rm7k_cpu_irq_init(int base)
......
......@@ -80,19 +80,12 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
}
static void rm9k_cpu_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
unmask_rm9k_irq(irq);
}
static struct irq_chip rm9k_irq_controller = {
.typename = "RM9000",
.ack = mask_rm9k_irq,
.mask = mask_rm9k_irq,
.mask_ack = mask_rm9k_irq,
.unmask = unmask_rm9k_irq,
.end = rm9k_cpu_irq_end,
};
static struct irq_chip rm9k_perfcounter_irq = {
......@@ -103,7 +96,6 @@ static struct irq_chip rm9k_perfcounter_irq = {
.mask = mask_rm9k_irq,
.mask_ack = mask_rm9k_irq,
.unmask = unmask_rm9k_irq,
.end = rm9k_cpu_irq_end,
};
unsigned int rm9000_perfcount_irq;
......
......@@ -50,12 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
irq_disable_hazard();
}
static void mips_cpu_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
unmask_mips_irq(irq);
}
static struct irq_chip mips_cpu_irq_controller = {
.typename = "MIPS",
.ack = mask_mips_irq,
......@@ -63,7 +57,6 @@ static struct irq_chip mips_cpu_irq_controller = {
.mask_ack = mask_mips_irq,
.unmask = unmask_mips_irq,
.eoi = unmask_mips_irq,
.end = mips_cpu_irq_end,
};
/*
......@@ -96,8 +89,6 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
mask_mips_mt_irq(irq);
}
#define mips_mt_cpu_irq_end mips_cpu_irq_end
static struct irq_chip mips_mt_cpu_irq_controller = {
.typename = "MIPS",
.startup = mips_mt_cpu_irq_startup,
......@@ -106,7 +97,6 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
.mask_ack = mips_mt_cpu_irq_ack,
.unmask = unmask_mips_mt_irq,
.eoi = unmask_mips_mt_irq,
.end = mips_mt_cpu_irq_end,
};
void __init mips_cpu_irq_init(int irq_base)
......
......@@ -44,19 +44,12 @@ void enable_lasat_irq(unsigned int irq_nr)
*lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
}
static void end_lasat_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_lasat_irq(irq);
}
static struct irq_chip lasat_irq_type = {
.typename = "Lasat",
.ack = disable_lasat_irq,
.mask = disable_lasat_irq,
.mask_ack = disable_lasat_irq,
.unmask = enable_lasat_irq,
.end = end_lasat_irq,
};
static inline int ls1bit32(unsigned int x)
......
......@@ -65,15 +65,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
value = OCELOT_FPGA_READ(INTMASK);
}
/*
* End IRQ processing
*/
static void end_cpci_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_cpci_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
......@@ -98,7 +89,6 @@ struct irq_chip cpci_irq_type = {
.mask = mask_cpci_irq,
.mask_ack = mask_cpci_irq,
.unmask = unmask_cpci_irq,
.end = end_cpci_irq,
};
void cpci_irq_init(void)
......
......@@ -59,15 +59,6 @@ static inline void unmask_uart_irq(unsigned int irq)
value = OCELOT_FPGA_READ(UART_INTMASK);
}
/*
* End IRQ processing
*/
static void end_uart_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
unmask_uart_irq(irq);
}
/*
* Interrupt handler for interrupts coming from the FPGA chip.
*/
......@@ -91,7 +82,6 @@ struct irq_chip uart_irq_type = {
.mask = mask_uart_irq,
.mask_ack = mask_uart_irq,
.unmask = unmask_uart_irq,
.end = end_uart_irq,
};
void uart_irq_init(void)
......
......@@ -158,20 +158,12 @@ int pnx8550_set_gic_priority(int irq, int priority)
return prev_priority;
}
static void end_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
unmask_irq(irq);
}
}
static struct irq_chip level_irq_type = {
.typename = "PNX Level IRQ",
.ack = mask_irq,
.mask = mask_irq,
.mask_ack = mask_irq,
.unmask = unmask_irq,
.end = end_irq,
};
static struct irqaction gic_action = {
......
......@@ -51,19 +51,12 @@ static void disable_local0_irq(unsigned int irq)
sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
}
static void end_local0_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_local0_irq(irq);
}
static struct irq_chip ip22_local0_irq_type = {
.typename = "IP22 local 0",
.ack = disable_local0_irq,
.mask = disable_local0_irq,
.mask_ack = disable_local0_irq,
.unmask = enable_local0_irq,
.end = end_local0_irq,
};
static void enable_local1_irq(unsigned int irq)
......@@ -79,19 +72,12 @@ void disable_local1_irq(unsigned int irq)
sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
}
static void end_local1_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_local1_irq(irq);
}
static struct irq_chip ip22_local1_irq_type = {
.typename = "IP22 local 1",
.ack = disable_local1_irq,
.mask = disable_local1_irq,
.mask_ack = disable_local1_irq,
.unmask = enable_local1_irq,
.end = end_local1_irq,
};
static void enable_local2_irq(unsigned int irq)
......@@ -107,19 +93,12 @@ void disable_local2_irq(unsigned int irq)
sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}
static void end_local2_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_local2_irq(irq);
}
static struct irq_chip ip22_local2_irq_type = {
.typename = "IP22 local 2",
.ack = disable_local2_irq,
.mask = disable_local2_irq,
.mask_ack = disable_local2_irq,
.unmask = enable_local2_irq,
.end = end_local2_irq,
};
static void enable_local3_irq(unsigned int irq)
......@@ -135,19 +114,12 @@ void disable_local3_irq(unsigned int irq)
sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}
static void end_local3_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_local3_irq(irq);
}
static struct irq_chip ip22_local3_irq_type = {
.typename = "IP22 local 3",
.ack = disable_local3_irq,
.mask = disable_local3_irq,
.mask_ack = disable_local3_irq,
.unmask = enable_local3_irq,
.end = end_local3_irq,
};
static void indy_local0_irqdispatch(void)
......
......@@ -332,13 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq)
intr_disconnect_level(cpu, swlevel);
}
static void end_bridge_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
irq_desc[irq].action)
enable_bridge_irq(irq);
}
static struct irq_chip bridge_irq_type = {
.typename = "bridge",
.startup = startup_bridge_irq,
......@@ -347,7 +340,6 @@ static struct irq_chip bridge_irq_type = {
.mask = disable_bridge_irq,
.mask_ack = disable_bridge_irq,
.unmask = enable_bridge_irq,
.end = end_bridge_irq,
};
void __devinit register_bridge_irq(unsigned int irq)
......
......@@ -180,10 +180,6 @@ static void disable_rt_irq(unsigned int irq)
{
}
static void end_rt_irq(unsigned int irq)
{
}
static struct irq_chip rt_irq_type = {
.typename = "SN HUB RT timer",
.ack = disable_rt_irq,
......@@ -191,7 +187,6 @@ static struct irq_chip rt_irq_type = {
.mask_ack = disable_rt_irq,
.unmask = enable_rt_irq,
.eoi = enable_rt_irq,
.end = end_rt_irq,
};
static struct irqaction rt_irqaction = {
......
......@@ -66,12 +66,10 @@
#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
#define TX4927_IRQ_ALL 0xffffffff
#endif
......@@ -82,12 +80,10 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
| TX4927_IRQ_WARN | TX4927_IRQ_EROR
// | TX4927_IRQ_CP0_INIT
// | TX4927_IRQ_CP0_ENABLE
// | TX4927_IRQ_CP0_DISABLE
// | TX4927_IRQ_CP0_ENDIRQ
// | TX4927_IRQ_PIC_INIT
// | TX4927_IRQ_PIC_ENABLE
// | TX4927_IRQ_PIC_DISABLE
// | TX4927_IRQ_PIC_ENDIRQ
// | TX4927_IRQ_INIT
// | TX4927_IRQ_NEST1
// | TX4927_IRQ_NEST2
......@@ -114,11 +110,9 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
static void tx4927_irq_cp0_enable(unsigned int irq);
static void tx4927_irq_cp0_disable(unsigned int irq);
static void tx4927_irq_cp0_end(unsigned int irq);
static void tx4927_irq_pic_enable(unsigned int irq);
static void tx4927_irq_pic_disable(unsigned int irq);
static void tx4927_irq_pic_end(unsigned int irq);
/*
* Kernel structs for all pic's
......@@ -131,7 +125,6 @@ static struct irq_chip tx4927_irq_cp0_type = {
.mask = tx4927_irq_cp0_disable,
.mask_ack = tx4927_irq_cp0_disable,
.unmask = tx4927_irq_cp0_enable,
.end = tx4927_irq_cp0_end,
};
#define TX4927_PIC_NAME "TX4927-PIC"
......@@ -141,7 +134,6 @@ static struct irq_chip tx4927_irq_pic_type = {
.mask = tx4927_irq_pic_disable,
.mask_ack = tx4927_irq_pic_disable,
.unmask = tx4927_irq_pic_enable,
.end = tx4927_irq_pic_end,
};
#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
......@@ -214,15 +206,6 @@ static void tx4927_irq_cp0_disable(unsigned int irq)
tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
}
static void tx4927_irq_cp0_end(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4927_irq_cp0_enable(irq);
}
}
/*
* Functions for pic
*/
......@@ -376,15 +359,6 @@ static void tx4927_irq_pic_disable(unsigned int irq)
tx4927_irq_pic_mask(irq), 0);
}
static void tx4927_irq_pic_end(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4927_irq_pic_enable(irq);
}
}
/*
* Main init functions
*/
......
......@@ -153,7 +153,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
......@@ -172,7 +171,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
......@@ -223,7 +221,6 @@ extern void mask_and_ack_8259A(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
......@@ -239,7 +236,6 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
.mask = toshiba_rbtx4927_irq_ioc_disable,
.mask_ack = toshiba_rbtx4927_irq_ioc_disable,
.unmask = toshiba_rbtx4927_irq_ioc_enable,
.end = toshiba_rbtx4927_irq_ioc_end,
};
#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
......@@ -388,23 +384,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
}
static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
toshiba_rbtx4927_irq_ioc_enable(irq);
}
}
/**********************************************************************************/
/* Functions for isa */
......
......@@ -39,11 +39,9 @@
static void tx4938_irq_cp0_enable(unsigned int irq);
static void tx4938_irq_cp0_disable(unsigned int irq);
static void tx4938_irq_cp0_end(unsigned int irq);
static void tx4938_irq_pic_enable(unsigned int irq);
static void tx4938_irq_pic_disable(unsigned int irq);
static void tx4938_irq_pic_end(unsigned int irq);
/**********************************************************************************/
/* Kernel structs for all pic's */
......@@ -56,7 +54,6 @@ static struct irq_chip tx4938_irq_cp0_type = {
.mask = tx4938_irq_cp0_disable,
.mask_ack = tx4938_irq_cp0_disable,
.unmask = tx4938_irq_cp0_enable,
.end = tx4938_irq_cp0_end,
};
#define TX4938_PIC_NAME "TX4938-PIC"
......@@ -66,7 +63,6 @@ static struct irq_chip tx4938_irq_pic_type = {
.mask = tx4938_irq_pic_disable,
.mask_ack = tx4938_irq_pic_disable,