Commit e3630db1 authored by eric miao's avatar eric miao Committed by Russell King
Browse files

[ARM] pxa: move GPIO IRQ specific code out of irq.c into gpio.c


Signed-off-by: default avatareric miao <eric.miao@marvell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0e037bbb
......@@ -16,6 +16,7 @@ extern void __init pxa_init_irq_low(void);
extern void __init pxa_init_irq_high(void);
extern void __init pxa_init_irq_gpio(int gpio_nr);
extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
extern void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int));
extern void __init pxa_init_gpio(int gpio_nr);
extern void __init pxa25x_init_irq(void);
extern void __init pxa27x_init_irq(void);
......
......@@ -14,6 +14,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
......@@ -165,3 +166,185 @@ void __init pxa_init_gpio(int gpio_nr)
gpiochip_add(&pxa_gpio_chip[i/32].chip);
}
}
/*
* PXA GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* Use this instead of directly setting GRER/GFER.
*/
static long GPIO_IRQ_rising_edge[4];
static long GPIO_IRQ_falling_edge[4];
static long GPIO_IRQ_mask[4];
static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
{
int gpio, idx;
gpio = IRQ_TO_GPIO(irq);
idx = gpio >> 5;
if (type == IRQ_TYPE_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or
* GPIOs set to alternate function or to output during probe
*/
if ((GPIO_IRQ_rising_edge[idx] |
GPIO_IRQ_falling_edge[idx] |
GPDR(gpio)) & GPIO_bit(gpio))
return 0;
if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
pxa_gpio_mode(gpio | GPIO_IN);
if (type & IRQ_TYPE_EDGE_RISING)
__set_bit(gpio, GPIO_IRQ_rising_edge);
else
__clear_bit(gpio, GPIO_IRQ_rising_edge);
if (type & IRQ_TYPE_EDGE_FALLING)
__set_bit(gpio, GPIO_IRQ_falling_edge);
else
__clear_bit(gpio, GPIO_IRQ_falling_edge);
GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
return 0;
}
/*
* GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
*/
static void pxa_ack_low_gpio(unsigned int irq)
{
GEDR0 = (1 << (irq - IRQ_GPIO0));
}
static void pxa_mask_low_gpio(unsigned int irq)
{
ICMR &= ~(1 << (irq - PXA_IRQ(0)));
}
static void pxa_unmask_low_gpio(unsigned int irq)
{
ICMR |= 1 << (irq - PXA_IRQ(0));
}
static struct irq_chip pxa_low_gpio_chip = {
.name = "GPIO-l",
.ack = pxa_ack_low_gpio,
.mask = pxa_mask_low_gpio,
.unmask = pxa_unmask_low_gpio,
.set_type = pxa_gpio_irq_type,
};
/*
* Demux handler for GPIO>=2 edge detect interrupts
*/
#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
int loop, bit, n;
unsigned long gedr[4];
do {
gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
GEDR0 = gedr[0]; GEDR1 = gedr[1];
GEDR2 = gedr[2]; GEDR3 = gedr[3];
loop = 0;
bit = find_first_bit(gedr, GEDR_BITS);
while (bit < GEDR_BITS) {
loop = 1;
n = PXA_GPIO_IRQ_BASE + bit;
desc_handle_irq(n, irq_desc + n);
bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
}
} while (loop);
}
static void pxa_ack_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
GEDR(gpio) = GPIO_bit(gpio);
}
static void pxa_mask_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
__clear_bit(gpio, GPIO_IRQ_mask);
GRER(gpio) &= ~GPIO_bit(gpio);
GFER(gpio) &= ~GPIO_bit(gpio);
}
static void pxa_unmask_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
int idx = gpio >> 5;
__set_bit(gpio, GPIO_IRQ_mask);
GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
}
static struct irq_chip pxa_muxed_gpio_chip = {
.name = "GPIO",
.ack = pxa_ack_muxed_gpio,
.mask = pxa_mask_muxed_gpio,
.unmask = pxa_unmask_muxed_gpio,
.set_type = pxa_gpio_irq_type,
};
void __init pxa_init_irq_gpio(int gpio_nr)
{
int irq, i;
pxa_last_gpio = gpio_nr - 1;
/* clear all GPIO edge detects */
for (i = 0; i < gpio_nr; i += 32) {
GFER(i) = 0;
GRER(i) = 0;
GEDR(i) = GEDR(i);
}
/* GPIO 0 and 1 must have their mask bit always set */
GPIO_IRQ_mask[0] = 3;
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
set_irq_chip(irq, &pxa_muxed_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Install handler for GPIO>=2 edge detect interrupts */
set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
pxa_init_gpio(gpio_nr);
}
void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int))
{
pxa_low_gpio_chip.set_wake = set_wake;
pxa_muxed_gpio_chip.set_wake = set_wake;
}
/*
* linux/arch/arm/mach-pxa/irq.c
*
* Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
* Generic PXA IRQ handling
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
......@@ -104,188 +104,6 @@ void __init pxa_init_irq_high(void)
}
#endif
/*
* PXA GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* Use this instead of directly setting GRER/GFER.
*/
static long GPIO_IRQ_rising_edge[4];
static long GPIO_IRQ_falling_edge[4];
static long GPIO_IRQ_mask[4];
static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
{
int gpio, idx;
gpio = IRQ_TO_GPIO(irq);
idx = gpio >> 5;
if (type == IRQ_TYPE_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or
* GPIOs set to alternate function or to output during probe
*/
if ((GPIO_IRQ_rising_edge[idx] |
GPIO_IRQ_falling_edge[idx] |
GPDR(gpio)) & GPIO_bit(gpio))
return 0;
if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
pxa_gpio_mode(gpio | GPIO_IN);
if (type & IRQ_TYPE_EDGE_RISING)
__set_bit(gpio, GPIO_IRQ_rising_edge);
else
__clear_bit(gpio, GPIO_IRQ_rising_edge);
if (type & IRQ_TYPE_EDGE_FALLING)
__set_bit(gpio, GPIO_IRQ_falling_edge);
else
__clear_bit(gpio, GPIO_IRQ_falling_edge);
GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
return 0;
}
/*
* GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
*/
static void pxa_ack_low_gpio(unsigned int irq)
{
GEDR0 = (1 << (irq - IRQ_GPIO0));
}
static void pxa_mask_low_gpio(unsigned int irq)
{
ICMR &= ~(1 << (irq - PXA_IRQ(0)));
}
static void pxa_unmask_low_gpio(unsigned int irq)
{
ICMR |= 1 << (irq - PXA_IRQ(0));
}
static struct irq_chip pxa_low_gpio_chip = {
.name = "GPIO-l",
.ack = pxa_ack_low_gpio,
.mask = pxa_mask_low_gpio,
.unmask = pxa_unmask_low_gpio,
.set_type = pxa_gpio_irq_type,
};
/*
* Demux handler for GPIO>=2 edge detect interrupts
*/
#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
int loop, bit, n;
unsigned long gedr[4];
do {
gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
GEDR0 = gedr[0]; GEDR1 = gedr[1];
GEDR2 = gedr[2]; GEDR3 = gedr[3];
loop = 0;
bit = find_first_bit(gedr, GEDR_BITS);
while (bit < GEDR_BITS) {
loop = 1;
n = PXA_GPIO_IRQ_BASE + bit;
desc_handle_irq(n, irq_desc + n);
bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
}
} while (loop);
}
static void pxa_ack_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
GEDR(gpio) = GPIO_bit(gpio);
}
static void pxa_mask_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
__clear_bit(gpio, GPIO_IRQ_mask);
GRER(gpio) &= ~GPIO_bit(gpio);
GFER(gpio) &= ~GPIO_bit(gpio);
}
static void pxa_unmask_muxed_gpio(unsigned int irq)
{
int gpio = irq - IRQ_GPIO(2) + 2;
int idx = gpio >> 5;
__set_bit(gpio, GPIO_IRQ_mask);
GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
}
static struct irq_chip pxa_muxed_gpio_chip = {
.name = "GPIO",
.ack = pxa_ack_muxed_gpio,
.mask = pxa_mask_muxed_gpio,
.unmask = pxa_unmask_muxed_gpio,
.set_type = pxa_gpio_irq_type,
};
void __init pxa_init_irq_gpio(int gpio_nr)
{
int irq, i;
pxa_last_gpio = gpio_nr - 1;
/* clear all GPIO edge detects */
for (i = 0; i < gpio_nr; i += 32) {
GFER(i) = 0;
GRER(i) = 0;
GEDR(i) = GEDR(i);
}
/* GPIO 0 and 1 must have their mask bit always set */
GPIO_IRQ_mask[0] = 3;
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
set_irq_chip(irq, &pxa_muxed_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Install handler for GPIO>=2 edge detect interrupts */
set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
pxa_init_gpio(gpio_nr);
}
void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int))
{
pxa_low_gpio_chip.set_wake = set_wake;
pxa_muxed_gpio_chip.set_wake = set_wake;
}
void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
{
pxa_internal_chip_low.set_wake = set_wake;
......
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