Commit e089d43f authored by Linus Torvalds's avatar Linus Torvalds

Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6:
  Use menuconfig objects: IDE
  sl82c105: Switch to ref counting API
  ide: remove ide_use_dma()
  ide: add missing validity checks for identify words 62 and 63
  ide: remove ide_dma_enable()
  sl82c105: add speedproc() method and MWDMA0/1 support
  cs5530/sc1200: add ->speedproc support
  cs5530/sc1200: DMA support cleanup
  ide: use ide_tune_dma() part #2
  cs5530/sc1200: add ->udma_filter methods
  ide: always disable DMA before tuning it
  pdc202xx_new: use ide_tune_dma()
  alim15x3: use ide_tune_dma()
  sis5513: PIO mode setup fixes
  serverworks: PIO mode setup fixes
  pdc202xx_old: rewrite mode programming code (v2)
parents 0e402c6e e0ff9cd1
......@@ -4,13 +4,10 @@
# Andre Hedrick <andre@linux-ide.org>
#
if BLOCK
menu "ATA/ATAPI/MFM/RLL support"
depends on HAS_IOMEM
config IDE
menuconfig IDE
tristate "ATA/ATAPI/MFM/RLL support"
depends on BLOCK
depends on HAS_IOMEM
---help---
If you say Y here, your kernel will be able to manage low cost mass
storage units such as ATA/(E)IDE and ATAPI units. The most common
......@@ -1099,8 +1096,4 @@ config BLK_DEV_HD_ONLY
config BLK_DEV_HD
def_bool BLK_DEV_HD_IDE || BLK_DEV_HD_ONLY
endif
endmenu
endif
endif # IDE
......@@ -1002,18 +1002,6 @@ static int cris_ide_build_dmatable (ide_drive_t *drive)
return 1; /* let the PIO routines handle this weirdness */
}
static int cris_config_drive_for_dma (ide_drive_t *drive)
{
u8 speed = ide_max_dma_mode(drive);
if (!speed)
return 0;
speed_cris_ide(drive, speed);
return ide_dma_enable(drive);
}
/*
* cris_dma_intr() is the handler for disk read/write DMA interrupts
*/
......@@ -1043,7 +1031,7 @@ static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
static int cris_dma_check(ide_drive_t *drive)
{
if (ide_use_dma(drive) && cris_config_drive_for_dma(drive))
if (ide_tune_dma(drive))
return 0;
return -1;
......
......@@ -670,41 +670,6 @@ int __ide_dma_good_drive (ide_drive_t *drive)
EXPORT_SYMBOL(__ide_dma_good_drive);
int ide_use_dma(ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = drive->hwif;
if ((id->capability & 1) == 0 || drive->autodma == 0)
return 0;
/* consult the list of known "bad" drives */
if (__ide_dma_bad_drive(drive))
return 0;
/* capable of UltraDMA modes */
if (id->field_valid & 4) {
if (hwif->ultra_mask & id->dma_ultra)
return 1;
}
/* capable of regular DMA modes */
if (id->field_valid & 2) {
if (hwif->mwdma_mask & id->dma_mword)
return 1;
if (hwif->swdma_mask & id->dma_1word)
return 1;
}
/* consult the list of known "good" drives */
if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
return 1;
return 0;
}
EXPORT_SYMBOL_GPL(ide_use_dma);
static const u8 xfer_mode_bases[] = {
XFER_UDMA_0,
XFER_MW_DMA_0,
......@@ -731,10 +696,12 @@ static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base)
mask &= 0x07;
break;
case XFER_MW_DMA_0:
mask = id->dma_mword & hwif->mwdma_mask;
if (id->field_valid & 2)
mask = id->dma_mword & hwif->mwdma_mask;
break;
case XFER_SW_DMA_0:
mask = id->dma_1word & hwif->swdma_mask;
if (id->field_valid & 2)
mask = id->dma_1word & hwif->swdma_mask;
break;
default:
BUG();
......@@ -783,8 +750,11 @@ int ide_tune_dma(ide_drive_t *drive)
{
u8 speed;
/* TODO: use only ide_max_dma_mode() */
if (!ide_use_dma(drive))
if ((drive->id->capability & 1) == 0 || drive->autodma == 0)
return 0;
/* consult the list of known "bad" drives */
if (__ide_dma_bad_drive(drive))
return 0;
speed = ide_max_dma_mode(drive);
......@@ -792,9 +762,10 @@ int ide_tune_dma(ide_drive_t *drive)
if (!speed)
return 0;
drive->hwif->speedproc(drive, speed);
if (drive->hwif->speedproc(drive, speed))
return 0;
return ide_dma_enable(drive);
return 1;
}
EXPORT_SYMBOL_GPL(ide_tune_dma);
......
......@@ -223,6 +223,7 @@ static ide_startstop_t ide_start_power_step(ide_drive_t *drive, struct request *
break;
if (drive->hwif->ide_dma_check == NULL)
break;
drive->hwif->dma_off_quietly(drive);
ide_set_dma(drive);
break;
}
......
......@@ -111,18 +111,6 @@ u8 ide_rate_filter(ide_drive_t *drive, u8 speed)
EXPORT_SYMBOL(ide_rate_filter);
int ide_dma_enable (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
struct hd_driveid *id = drive->id;
return ((int) ((((id->dma_ultra >> 8) & hwif->ultra_mask) ||
((id->dma_mword >> 8) & hwif->mwdma_mask) ||
((id->dma_1word >> 8) & hwif->swdma_mask)) ? 1 : 0));
}
EXPORT_SYMBOL(ide_dma_enable);
int ide_use_fast_pio(ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
......
......@@ -910,6 +910,7 @@ int set_using_dma(ide_drive_t *drive, int arg)
err = 0;
if (arg) {
hwif->dma_off_quietly(drive);
if (ide_set_dma(drive) || hwif->ide_dma_on(drive))
err = -EIO;
} else
......
......@@ -455,28 +455,6 @@ static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
return (ide_config_drive_speed(drive, speed));
}
/**
* config_chipset_for_dma - set up DMA mode
* @drive: drive to configure for
*
* Place a drive into DMA mode and tune the chipset for
* the selected speed.
*
* Returns true if DMA mode can be used
*/
static int config_chipset_for_dma (ide_drive_t *drive)
{
u8 speed = ide_max_dma_mode(drive);
if (!(speed))
return 0;
(void) ali15x3_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
/**
* ali15x3_config_drive_for_dma - configure for DMA
* @drive: drive to configure
......@@ -487,48 +465,14 @@ static int config_chipset_for_dma (ide_drive_t *drive)
static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
struct hd_driveid *id = drive->id;
if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
goto ata_pio;
drive->init_speed = 0;
if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
/* Consult the list of known "bad" drives */
if (__ide_dma_bad_drive(drive))
goto ata_pio;
if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
if (id->dma_ultra & hwif->ultra_mask) {
/* Force if Capable UltraDMA */
int dma = config_chipset_for_dma(drive);
if ((id->field_valid & 2) && !dma)
goto try_dma_modes;
}
} else if (id->field_valid & 2) {
try_dma_modes:
if ((id->dma_mword & hwif->mwdma_mask) ||
(id->dma_1word & hwif->swdma_mask)) {
/* Force if Capable regular DMA modes */
if (!config_chipset_for_dma(drive))
goto ata_pio;
}
} else if (__ide_dma_good_drive(drive) &&
(id->eide_dma_time < 150)) {
/* Consult the list of known "good" drives */
if (!config_chipset_for_dma(drive))
goto ata_pio;
} else {
goto ata_pio;
}
} else {
ata_pio:
hwif->tuneproc(drive, 255);
return -1;
}
if (ide_tune_dma(drive))
return 0;
return 0;
ali15x3_tune_drive(drive, 255);
return -1;
}
/**
......@@ -739,7 +683,8 @@ static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
return;
}
hwif->atapi_dma = 1;
if (m5229_revision > 0x20)
hwif->atapi_dma = 1;
if (m5229_revision <= 0x20)
hwif->ultra_mask = 0x00; /* no udma */
......
......@@ -352,22 +352,9 @@ static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
return ide_config_drive_speed(drive, speed);
}
static int config_chipset_for_dma (ide_drive_t *drive)
{
u8 speed = ide_max_dma_mode(drive);
if (!speed)
return 0;
if (cmd64x_tune_chipset(drive, speed))
return 0;
return ide_dma_enable(drive);
}
static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
{
if (ide_use_dma(drive) && config_chipset_for_dma(drive))
if (ide_tune_dma(drive))
return 0;
if (ide_use_fast_pio(drive))
......
/*
* linux/drivers/ide/pci/cs5530.c Version 0.7 Sept 10, 2002
* linux/drivers/ide/pci/cs5530.c Version 0.73 Mar 10 2007
*
* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
* Ditto of GNU General Public License.
*
* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
*
* May be copied or modified under the terms of the GNU General Public License
*
* Development of this chipset driver was funded
......@@ -62,6 +62,14 @@ static unsigned int cs5530_pio_timings[2][5] = {
#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
static void cs5530_tunepio(ide_drive_t *drive, u8 pio)
{
unsigned long basereg = CS5530_BASEREG(drive->hwif);
unsigned int format = (inl(basereg + 4) >> 31) & 1;
outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
}
/**
* cs5530_tuneproc - select/set PIO modes
*
......@@ -74,98 +82,78 @@ static unsigned int cs5530_pio_timings[2][5] = {
static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autotune" */
{
ide_hwif_t *hwif = HWIF(drive);
unsigned int format;
unsigned long basereg = CS5530_BASEREG(hwif);
static u8 modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
if (!cs5530_set_xfer_mode(drive, modes[pio])) {
format = (inl(basereg + 4) >> 31) & 1;
outl(cs5530_pio_timings[format][pio],
basereg+(drive->select.b.unit<<3));
if (cs5530_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
cs5530_tunepio(drive, pio);
}
/**
* cs5530_udma_filter - UDMA filter
* @drive: drive
*
* cs5530_udma_filter() does UDMA mask filtering for the given drive
* taking into the consideration capabilities of the mate device.
*
* The CS5530 specifies that two drives sharing a cable cannot mix
* UDMA/MDMA. It has to be one or the other, for the pair, though
* different timings can still be chosen for each drive. We could
* set the appropriate timing bits on the fly, but that might be
* a bit confusing. So, for now we statically handle this requirement
* by looking at our mate drive to see what it is capable of, before
* choosing a mode for our own drive.
*
* Note: This relies on the fact we never fail from UDMA to MWDMA2
* but instead drop to PIO.
*/
static u8 cs5530_udma_filter(ide_drive_t *drive)
{
ide_hwif_t *hwif = drive->hwif;
ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
struct hd_driveid *mateid = mate->id;
u8 mask = hwif->ultra_mask;
if (mate->present == 0)
goto out;
if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
goto out;
if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
mask = 0;
}
out:
return mask;
}
/**
* cs5530_config_dma - select/set DMA and UDMA modes
* cs5530_config_dma - set DMA/UDMA mode
* @drive: drive to tune
*
* cs5530_config_dma() handles selection/setting of DMA/UDMA modes
* for both the chipset and drive. The CS5530 has limitations about
* mixing DMA/UDMA on the same cable.
* cs5530_config_dma() handles setting of DMA/UDMA mode
* for both the chipset and drive.
*/
static int cs5530_config_dma (ide_drive_t *drive)
static int cs5530_config_dma(ide_drive_t *drive)
{
int udma_ok = 1, mode = 0;
ide_hwif_t *hwif = HWIF(drive);
int unit = drive->select.b.unit;
ide_drive_t *mate = &hwif->drives[unit^1];
struct hd_driveid *id = drive->id;
unsigned int reg, timings = 0;
unsigned long basereg;
if (ide_tune_dma(drive))
return 0;
/*
* Default to DMA-off in case we run into trouble here.
*/
hwif->dma_off_quietly(drive);
return 1;
}
/*
* The CS5530 specifies that two drives sharing a cable cannot
* mix UDMA/MDMA. It has to be one or the other, for the pair,
* though different timings can still be chosen for each drive.
* We could set the appropriate timing bits on the fly,
* but that might be a bit confusing. So, for now we statically
* handle this requirement by looking at our mate drive to see
* what it is capable of, before choosing a mode for our own drive.
*
* Note: This relies on the fact we never fail from UDMA to MWDMA_2
* but instead drop to PIO
*/
if (mate->present) {
struct hd_driveid *mateid = mate->id;
if (mateid && (mateid->capability & 1) &&
!__ide_dma_bad_drive(mate)) {
if ((mateid->field_valid & 4) &&
(mateid->dma_ultra & 7))
udma_ok = 1;
else if ((mateid->field_valid & 2) &&
(mateid->dma_mword & 7))
udma_ok = 0;
else
udma_ok = 1;
}
}
static int cs5530_tune_chipset(ide_drive_t *drive, u8 mode)
{
unsigned long basereg;
unsigned int reg, timings = 0;
/*
* Now see what the current drive is capable of,
* selecting UDMA only if the mate said it was ok.
*/
if (id && (id->capability & 1) && drive->autodma &&
!__ide_dma_bad_drive(drive)) {
if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
if (id->dma_ultra & 4)
mode = XFER_UDMA_2;
else if (id->dma_ultra & 2)
mode = XFER_UDMA_1;
else if (id->dma_ultra & 1)
mode = XFER_UDMA_0;
}
if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
if (id->dma_mword & 4)
mode = XFER_MW_DMA_2;
else if (id->dma_mword & 2)
mode = XFER_MW_DMA_1;
else if (id->dma_mword & 1)
mode = XFER_MW_DMA_0;
}
}
mode = ide_rate_filter(drive, mode);
/*
* Tell the drive to switch to the new mode; abort on failure.
*/
if (!mode || cs5530_set_xfer_mode(drive, mode))
if (cs5530_set_xfer_mode(drive, mode))
return 1; /* failure */
/*
......@@ -178,14 +166,21 @@ static int cs5530_config_dma (ide_drive_t *drive)
case XFER_MW_DMA_0: timings = 0x00077771; break;
case XFER_MW_DMA_1: timings = 0x00012121; break;
case XFER_MW_DMA_2: timings = 0x00002020; break;
case XFER_PIO_4:
case XFER_PIO_3:
case XFER_PIO_2:
case XFER_PIO_1:
case XFER_PIO_0:
cs5530_tunepio(drive, mode - XFER_PIO_0);
return 0;
default:
BUG();
break;
}
basereg = CS5530_BASEREG(hwif);
basereg = CS5530_BASEREG(drive->hwif);
reg = inl(basereg + 4); /* get drive0 config register */
timings |= reg & 0x80000000; /* preserve PIO format bit */
if (unit == 0) { /* are we configuring drive0? */
if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
outl(timings, basereg + 4); /* write drive0 config register */
} else {
if (timings & 0x00100000)
......@@ -311,6 +306,8 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
hwif->serialized = hwif->mate->serialized = 1;
hwif->tuneproc = &cs5530_tuneproc;
hwif->speedproc = &cs5530_tune_chipset;
basereg = CS5530_BASEREG(hwif);
d0_timings = inl(basereg + 0);
if (CS5530_BAD_PIO(d0_timings)) {
......@@ -332,6 +329,7 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
hwif->ultra_mask = 0x07;
hwif->mwdma_mask = 0x07;
hwif->udma_filter = cs5530_udma_filter;
hwif->ide_dma_check = &cs5530_config_dma;
if (!noautodma)
hwif->autodma = 1;
......
......@@ -463,25 +463,6 @@ static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
return ide_config_drive_speed(drive, speed);
}
/**
* config_chipset_for_dma - configure for DMA
* @drive: drive to configure
*
* Called by the IDE layer when it wants the timings set up.
*/
static int config_chipset_for_dma (ide_drive_t *drive)
{
u8 speed = ide_max_dma_mode(drive);
if (speed == 0)
return 0;
it821x_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
/**
* it821x_configure_drive_for_dma - set up for DMA transfers
* @drive: drive we are going to set up
......@@ -494,7 +475,7 @@ static int config_chipset_for_dma (ide_drive_t *drive)
static int it821x_config_drive_for_dma (ide_drive_t *drive)
{
if (ide_use_dma(drive) && config_chipset_for_dma(drive))
if (ide_tune_dma(drive))
return 0;
it821x_tuneproc(drive, 255);
......
......@@ -228,38 +228,11 @@ static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
return get_indexed_reg(hwif, 0x0b) & 0x04;
}
static int config_chipset_for_dma(ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = HWIF(drive);
u8 speed;
if (id->capability & 4) {
/*
* Set IORDY_EN & PREFETCH_EN (this seems to have
* NO real effect since this register is reloaded
* by hardware when the transfer mode is selected)
*/
u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
tmp = get_indexed_reg(hwif, 0x13 + adj);
set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
}
speed = ide_max_dma_mode(drive);
if (!speed)
return 0;
(void) hwif->speedproc(drive, speed);
return ide_dma_enable(drive);
}
static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
{
drive->init_speed = 0;
if (ide_use_dma(drive) && config_chipset_for_dma(drive))
if (ide_tune_dma(drive))
return 0;
if (ide_use_fast_pio(drive))
......
/*
* linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
* linux/drivers/ide/pci/pdc202xx_old.c Version 0.50 Mar 3, 2007
*
* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
* Copyright (C) 2006-2007 MontaVista Software, Inc.
* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
*
* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
* compiled into the kernel if you have more than one card installed.
......@@ -60,45 +61,7 @@ static const char *pdc_quirk_drives[] = {
NULL
};
/* A Register */
#define SYNC_ERRDY_EN 0xC0
#define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
#define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
#define IORDY_EN 0x20 /* PIO: IOREADY */
#define PREFETCH_EN 0x10 /* PIO: PREFETCH */
#define PA3 0x08 /* PIO"A" timing */
#define PA2 0x04 /* PIO"A" timing */
#define PA1 0x02 /* PIO"A" timing */
#define PA0 0x01 /* PIO"A" timing */
/* B Register */
#define MB2 0x80 /* DMA"B" timing */
#define MB1 0x40 /* DMA"B" timing */
#define MB0 0x20 /* DMA"B" timing */
#define PB4 0x10 /* PIO_FORCE 1:0 */
#define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
#define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
#define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
#define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
/* C Register */
#define IORDYp_NO_SPEED 0x4F
#define SPEED_DIS 0x0F
#define DMARQp 0x80
#define IORDYp 0x40
#define DMAR_EN 0x20
#define DMAW_EN 0x10
#define MC3 0x08 /* DMA"C" timing */
#define MC2 0x04 /* DMA"C" timing */
#define MC1 0x02 /* DMA"C" timing */