Commit dbc895f9 authored by Graf Yang's avatar Graf Yang Committed by Bryan Wu

Blackfin arch: smp patch cleanup from LKML review

1. Use inline get_l1_... functions instead of macro
2. Fix compile issue about smp barrier functions
Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent f994607a
......@@ -9,4 +9,79 @@
#include <mach/mem_map.h>
#ifndef __ASSEMBLY__
#ifdef CONFIG_SMP
static inline ulong get_l1_scratch_start_cpu(int cpu)
{
return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
}
static inline ulong get_l1_code_start_cpu(int cpu)
{
return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;
}
static inline ulong get_l1_data_a_start_cpu(int cpu)
{
return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
}
static inline ulong get_l1_data_b_start_cpu(int cpu)
{
return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
}
static inline ulong get_l1_scratch_start(void)
{
return get_l1_scratch_start_cpu(blackfin_core_id());
}
static inline ulong get_l1_code_start(void)
{
return get_l1_code_start_cpu(blackfin_core_id());
}
static inline ulong get_l1_data_a_start(void)
{
return get_l1_data_a_start_cpu(blackfin_core_id());
}
static inline ulong get_l1_data_b_start(void)
{
return get_l1_data_b_start_cpu(blackfin_core_id());
}
#else /* !CONFIG_SMP */
static inline ulong get_l1_scratch_start_cpu(int cpu)
{
return L1_SCRATCH_START;
}
static inline ulong get_l1_code_start_cpu(int cpu)
{
return L1_CODE_START;
}
static inline ulong get_l1_data_a_start_cpu(int cpu)
{
return L1_DATA_A_START;
}
static inline ulong get_l1_data_b_start_cpu(int cpu)
{
return L1_DATA_B_START;
}
static inline ulong get_l1_scratch_start(void)
{
return get_l1_scratch_start_cpu(0);
}
static inline ulong get_l1_code_start(void)
{
return get_l1_code_start_cpu(0);
}
static inline ulong get_l1_data_a_start(void)
{
return get_l1_data_a_start_cpu(0);
}
static inline ulong get_l1_data_b_start(void)
{
return get_l1_data_b_start_cpu(0);
}
#endif /* CONFIG_SMP */
#endif /* __ASSEMBLY__ */
#endif /* _MEM_MAP_H_ */
......@@ -32,6 +32,8 @@
#define raw_smp_processor_id() blackfin_core_id()
extern char coreb_trampoline_start, coreb_trampoline_end;
struct corelock_slot {
int lock;
};
......
......@@ -66,10 +66,13 @@ asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
# define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
# define smp_rmb() do { barrier(); smp_check_barrier(); } while (0)
# define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0)
#define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
#else
# define smp_mb() barrier()
# define smp_rmb() barrier()
# define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#endif
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
......@@ -120,8 +123,6 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
(unsigned long)(n), sizeof(*(ptr))))
#define smp_read_barrier_depends() smp_check_barrier()
#else /* !CONFIG_SMP */
#define smp_mb() barrier()
......@@ -192,6 +193,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
*/
#include <asm/l1layout.h>
#include <asm/mem_map.h>
asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
......
......@@ -99,6 +99,8 @@ EXPORT_SYMBOL(__raw_bit_test_set_asm);
EXPORT_SYMBOL(__raw_bit_test_clear_asm);
EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
EXPORT_SYMBOL(__raw_uncached_fetch_asm);
#ifdef __ARCH_SYNC_CORE_DCACHE
EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
#endif
#endif
......@@ -25,6 +25,7 @@
#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#include <asm/mem_map.h>
#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
......
......@@ -27,6 +27,7 @@
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#include <asm/mem_map.h>
u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
......
......@@ -39,6 +39,7 @@
#include <asm/blackfin.h>
#include <asm/fixed_code.h>
#include <asm/mem_map.h>
asmlinkage void ret_from_fork(void);
......
......@@ -45,6 +45,7 @@
#include <asm/asm-offsets.h>
#include <asm/dma.h>
#include <asm/fixed_code.h>
#include <asm/mem_map.h>
#define TEXT_OFFSET 0
/*
......
......@@ -99,15 +99,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -99,15 +99,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -168,15 +168,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -176,15 +176,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -104,15 +104,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -108,15 +108,6 @@
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#define GET_PDA_SAFE(preg) \
preg.l = _cpu_pda; \
preg.h = _cpu_pda;
......
......@@ -85,47 +85,7 @@
#define L1_SCRATCH_START COREA_L1_SCRATCH_START
#define L1_SCRATCH_LENGTH 0x1000
#ifndef __ASSEMBLY__
#ifdef CONFIG_SMP
#define get_l1_scratch_start_cpu(cpu) \
({ unsigned long __addr; \
__addr = (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;\
__addr; })
#define get_l1_code_start_cpu(cpu) \
({ unsigned long __addr; \
__addr = (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; \
__addr; })
#define get_l1_data_a_start_cpu(cpu) \
({ unsigned long __addr; \
__addr = (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;\
__addr; })
#define get_l1_data_b_start_cpu(cpu) \
({ unsigned long __addr; \
__addr = (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;\
__addr; })
#define get_l1_scratch_start() get_l1_scratch_start_cpu(blackfin_core_id())
#define get_l1_code_start() get_l1_code_start_cpu(blackfin_core_id())
#define get_l1_data_a_start() get_l1_data_a_start_cpu(blackfin_core_id())
#define get_l1_data_b_start() get_l1_data_b_start_cpu(blackfin_core_id())
#else /* !CONFIG_SMP */
#define get_l1_scratch_start_cpu(cpu) L1_SCRATCH_START
#define get_l1_code_start_cpu(cpu) L1_CODE_START
#define get_l1_data_a_start_cpu(cpu) L1_DATA_A_START
#define get_l1_data_b_start_cpu(cpu) L1_DATA_B_START
#define get_l1_scratch_start() L1_SCRATCH_START
#define get_l1_code_start() L1_CODE_START
#define get_l1_data_a_start() L1_DATA_A_START
#define get_l1_data_b_start() L1_DATA_B_START
#endif /* !CONFIG_SMP */
#else /* __ASSEMBLY__ */
#ifdef __ASSEMBLY__
/*
* The following macros both return the address of the PDA for the
......
......@@ -27,11 +27,6 @@
#include <asm/smp.h>
#include <asm/dma.h>
#define COREB_SRAM_BASE 0xff600000
#define COREB_SRAM_SIZE 0x4000
extern char coreb_trampoline_start, coreb_trampoline_end;
static DEFINE_SPINLOCK(boot_lock);
static cpumask_t cpu_callin_map;
......@@ -54,15 +49,15 @@ void __init platform_prepare_cpus(unsigned int max_cpus)
int len;
len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
BUG_ON(len > COREB_SRAM_SIZE);
BUG_ON(len > L1_CODE_LENGTH);
dma_memcpy((void *)COREB_SRAM_BASE, &coreb_trampoline_start, len);
dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
/* Both cores ought to be present on a bf561! */
cpu_set(0, cpu_present_map); /* CoreA */
cpu_set(1, cpu_present_map); /* CoreB */
printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_SRAM_BASE);
printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
}
int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
......
......@@ -39,6 +39,7 @@
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <asm/blackfin.h>
#include <asm/mem_map.h>
#include "blackfin_sram.h"
static DEFINE_PER_CPU(spinlock_t, l1sram_lock) ____cacheline_aligned_in_smp;
......
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