Commit db5b7169 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] Remove MT_DEVICE_IXP2000 and associated definitions



As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant.  Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 40df2d1d
......@@ -60,10 +60,9 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
#define MT_DEVICE 0
#define MT_DEVICE_NONSHARED 1
#define MT_DEVICE_CACHED 2
#define MT_DEVICE_IXP2000 3
#define MT_DEVICE_WC 4
#define MT_DEVICE_WC 3
/*
* types 5 onwards can be found in asm/mach/map.h and are undefined
* types 4 onwards can be found in asm/mach/map.h and are undefined
* for ioremap
*/
......
......@@ -18,16 +18,15 @@ struct map_desc {
unsigned int type;
};
/* types 0-4 are defined in asm/io.h */
#define MT_CACHECLEAN 5
#define MT_MINICLEAN 6
#define MT_LOW_VECTORS 7
#define MT_HIGH_VECTORS 8
#define MT_MEMORY 9
#define MT_ROM 10
/* types 0-3 are defined in asm/io.h */
#define MT_CACHECLEAN 4
#define MT_MINICLEAN 5
#define MT_LOW_VECTORS 6
#define MT_HIGH_VECTORS 7
#define MT_MEMORY 8
#define MT_ROM 9
#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
#ifdef CONFIG_MMU
extern void iotable_init(struct map_desc *, int);
......
......@@ -184,7 +184,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
#define L_PTE_MT_MASK (0x0f << 2)
......
......@@ -84,64 +84,57 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
.virtual = IXP2000_CAP_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
.length = IXP2000_CAP_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_INTCTL_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
.length = IXP2000_INTCTL_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_PCI_CREG_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
.length = IXP2000_PCI_CREG_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_PCI_CSR_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
.length = IXP2000_PCI_CSR_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_MSF_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
.length = IXP2000_MSF_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
.length = IXP2000_SCRATCH_RING_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_SRAM0_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
.length = IXP2000_SRAM0_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_PCI_IO_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
.length = IXP2000_PCI_IO_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
.length = IXP2000_PCI_CFG0_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
.length = IXP2000_PCI_CFG1_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}
};
void __init ixp2000_map_io(void)
{
/*
* On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
* XCB=101 (to avoid triggering erratum #66), and given that
* this mode speeds up I/O accesses and we have write buffer
* flushes in the right places anyway, it doesn't hurt to use
* XCB=101 for all IXP2000s.
*/
iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
/* Set slowport to 8-bit mode. */
......
......@@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
.virtual = ENP2611_CALEB_VIRT_BASE,
.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
.length = ENP2611_CALEB_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = ENP2611_PM3386_0_VIRT_BASE,
.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
.length = ENP2611_PM3386_0_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}, {
.virtual = ENP2611_PM3386_1_VIRT_BASE,
.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
.length = ENP2611_PM3386_1_SIZE,
.type = MT_DEVICE_IXP2000,
.type = MT_DEVICE,
}
};
......
......@@ -41,13 +41,7 @@
* Most of the registers are clumped in 4K regions spread throughout
* the 0xc0000000 -> 0xc0100000 address range, but we just map in
* the whole range using a single 1 MB section instead of small
* 4K pages. This has two advantages for us:
*
* 1) We use only one TLB entry for large number of on-chip I/O devices.
*
* 2) We can easily set the Section attributes to XCB=101 on the IXP2400
* as required per erratum #66. We accomplish this by using a
* new MT_IXP2000_DEVICE memory type with the bits set as required.
* 4K pages.
*
* CAP stands for CSR Access Proxy.
*
......
......@@ -204,13 +204,6 @@ static struct mem_type mem_types[] = {
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
.domain = DOMAIN_IO,
},
[MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_IXP2000,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
PMD_SECT_TEX(1),
.domain = DOMAIN_IO,
},
[MT_DEVICE_WC] = { /* ioremap_wc */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
.prot_l1 = PMD_TYPE_TABLE,
......
......@@ -119,7 +119,7 @@
.long 0x00 @ unused
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ L_PTE_MT_DEV_IXP2000
.long 0x00 @ unused
.long 0x00 @ unused
.long 0x00 @ unused
.endm
......
......@@ -360,7 +360,7 @@ cpu_xsc3_mt_table:
.long 0x00 @ unused
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ L_PTE_MT_DEV_IXP2000 (not present)
.long 0x00 @ unused
.long 0x00 @ unused
.long 0x00 @ unused
......
......@@ -443,7 +443,7 @@ cpu_xscale_mt_table:
.long 0x00 @ unused
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
.long 0x00 @ L_PTE_MT_DEV_NONSHARED
.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_IXP2000
.long 0x00 @ unused
.long 0x00 @ unused
.long 0x00 @ unused
......
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