Commit d94f944e authored by Anton Vorontsov's avatar Anton Vorontsov

ARM: cns3xxx: Add basic support for Cavium Networks CNS3xxx processors

This patch adds very basic support for ECONA CNS3xxx ARM11 MPcore
(ARMv6) dual-core processors.

Note that SMP is not yet supported, as well as many peripheral
devices. Support for these features will be added later.
Signed-off-by: default avatarAnton Vorontsov <avorontsov@mvista.com>
parent ea5ce655
......@@ -586,6 +586,12 @@ F: drivers/mtd/nand/bcm_umi_bch.c
F: drivers/mtd/nand/bcm_umi_hamming.c
F: drivers/mtd/nand/nand_bcm_umi.h
ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
M: Anton Vorontsov <avorontsov@mvista.com>
S: Maintained
F: arch/arm/mach-cns3xxx/
T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
M: Hartley Sweeten <hsweeten@visionengravers.com>
M: Ryan Mallon <ryan@bluewatersys.com>
......
......@@ -297,6 +297,15 @@ config ARCH_CLPS711X
help
Support for Cirrus Logic 711x/721x based boards.
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
select CPU_V6
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select ARM_GIC
help
Support for Cavium Networks CNS3XXX platform.
config ARCH_GEMINI
bool "Cortina Systems Gemini"
select CPU_FA526
......@@ -817,6 +826,8 @@ source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-dove/Kconfig"
......
......@@ -121,6 +121,7 @@ machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_BCMRING) := bcmring
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_DOVE) := dove
machine-$(CONFIG_ARCH_EBSA110) := ebsa110
......
menu "CNS3XXX platform type"
depends on ARCH_CNS3XXX
endmenu
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00C00000
/*
* Copyright 1999 - 2003 ARM Limited
* Copyright 2000 Deep Blue Solutions Ltd
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
#include <mach/cns3xxx.h>
#include "core.h"
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
.virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_GPIOA_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_GPIOB_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_MISC_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_PM_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
void __init cns3xxx_map_io(void)
{
iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
}
/* used by entry-macro.S */
void __iomem *gic_cpu_base_addr;
void __init cns3xxx_init_irq(void)
{
gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
gic_cpu_init(0, gic_cpu_base_addr);
}
void cns3xxx_power_off(void)
{
u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
u32 clkctrl;
printk(KERN_INFO "powering system down...\n");
clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
clkctrl &= 0xfffff1ff;
clkctrl |= (0x5 << 9); /* Hibernate */
writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
}
/*
* Timer
*/
static void __iomem *cns3xxx_tmr1;
static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
int pclk = cns3xxx_cpu_clock() / 8;
int reload;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
reload = pclk * 20 / (3 * HZ) * 0x25000;
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctrl |= (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = 0;
}
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
}
static int cns3xxx_timer_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
return 0;
}
static struct clock_event_device cns3xxx_tmr1_clockevent = {
.name = "cns3xxx timer1",
.shift = 8,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = cns3xxx_timer_set_mode,
.set_next_event = cns3xxx_timer_set_next_event,
.rating = 350,
.cpumask = cpu_all_mask,
};
static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
{
cns3xxx_tmr1_clockevent.irq = timer_irq;
cns3xxx_tmr1_clockevent.mult =
div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
cns3xxx_tmr1_clockevent.shift);
cns3xxx_tmr1_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
cns3xxx_tmr1_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
clockevents_register_device(&cns3xxx_tmr1_clockevent);
}
/*
* IRQ handler for the timer
*/
static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
u32 val;
/* Clear the interrupt */
val = readl(stat);
writel(val & ~(1 << 2), stat);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction cns3xxx_timer_irq = {
.name = "timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = cns3xxx_timer_interrupt,
};
/*
* Set up the clock source and clock events devices
*/
static void __init __cns3xxx_timer_init(unsigned int timer_irq)
{
u32 val;
u32 irq_mask;
/*
* Initialise to a known state (all timers off)
*/
/* disable timer1 and timer2 */
writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* stop free running timer3 */
writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
/* timer1 */
writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
/* mask irq, non-mask timer1 overflow */
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask &= ~(1 << 2);
irq_mask |= 0x03;
writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* down counter */
val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
val |= (1 << 9);
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* timer2 */
writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
/* mask irq */
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
/* down counter */
val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
val |= (1 << 10);
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* Make irqs happen for the system timer */
setup_irq(timer_irq, &cns3xxx_timer_irq);
cns3xxx_clockevents_init(timer_irq);
}
static void __init cns3xxx_timer_init(void)
{
cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
}
struct sys_timer cns3xxx_timer = {
.init = cns3xxx_timer_init,
};
/*
* Copyright 2000 Deep Blue Solutions Ltd
* Copyright 2004 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __CNS3XXX_CORE_H
#define __CNS3XXX_CORE_H
extern void __iomem *gic_cpu_base_addr;
extern struct sys_timer cns3xxx_timer;
void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);
void cns3xxx_pwr_power_up(unsigned int block);
void cns3xxx_pwr_power_down(unsigned int block);
#endif /* __CNS3XXX_CORE_H */
This diff is collapsed.
/*
* Debugging macro include header
*
* Copyright 1994-1999 Russell King
* Copyright 2008 Cavium Networks
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
movne \rx, #0xf0000000 @ virtual base
orr \rx, \rx, #0x00009000
.endm
#include <asm/hardware/debug-pl01x.S>
/*
* Low-level IRQ helper macros for Cavium Networks platforms
*
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
#include <asm/hardware/gic.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an interrupt if it's
* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
*
* A simple read from the controller will tell us the number of the highest
* priority enabled interrupt. We then just need to check whether it is in the
* valid range for an IRQ (30-1020 inclusive).
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt on the
* controller, since this requires the original irqstat value which
* we won't easily be able to recreate later.
*/
.macro test_for_ipi, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #16
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
/*
* This file contains the hardware definitions of the Cavium Networks boards.
*
* Copyright 2003 ARM Limited.
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#include <asm/sizes.h>
/* macro to get at IO space when running virtually */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#define pcibios_assign_all_busses() 1
#endif
/*
* Copyright 2008 Cavium Networks
* Copyright 2003 ARM Limited
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_IO_H
#define __MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif
/*
* Copyright 2000 Deep Blue Solutions Ltd.
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
#define IRQ_TC11MP_GIC_START 32
#include <mach/cns3xxx.h>
#ifndef NR_IRQS
#error "NR_IRQS not defined by the board-specific files"
#endif
#endif
/*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_MEMORY_H
#define __MACH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
#define __phys_to_bus(x) ((x) + PHYS_OFFSET)
#define __bus_to_phys(x) ((x) - PHYS_OFFSET)
#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
#endif
/*
* Copyright 2000 Deep Blue Solutions Ltd
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_SYSTEM_H
#define __MACH_SYSTEM_H
#include <linux/io.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
void arch_reset(char mode, const char *cmd);
#endif
/*
* Cavium Networks architecture timex specifications
*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#define CLOCK_TICK_RATE (50000000 / 16)
/*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/cns3xxx.h>
#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
/*
* Return the UART base address
*/
static inline unsigned long get_uart_base(void)
{
if (machine_is_cns3420vb())
return CNS3XXX_UART0_BASE;
else
return 0;
}
/*
* This does not append a newline
*/
static inline void putc(int c)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 5))
barrier();
AMBA_UART_DR(base) = c;
}
static inline void flush(void)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
/*
* Copyright 2000 Russell King.
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#define VMALLOC_END 0xd8000000
/*
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
void cns3xxx_pwr_clk_en(unsigned int block)
{
PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
}
void cns3xxx_pwr_power_up(unsigned int block)
{
PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
/* Wait for 300us for the PLL output clock locked. */
udelay(300);
};
void cns3xxx_pwr_power_down(unsigned int block)
{
/* write '1' to power down */
PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
};
static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
/*
* bit 0, 28, 29 => program low to reset,
* the other else program low and then high
*/
if (block & 0x30000001) {
PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
} else {
PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
}
}
void cns3xxx_pwr_soft_rst(unsigned int block)
{
static unsigned int soft_reset;
if (soft_reset & block) {
/* SPI/I2C/GPIO use the same block, reset once. */
return;
} else {
soft_reset |= block;
}
cns3xxx_pwr_soft_rst_force(block);
}
void arch_reset(char mode, const char *cmd)
{
/*
* To reset, we hit the on-board reset register
* in the system FPGA.
*/
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
}
/*
* cns3xxx_cpu_clock - return CPU/L2 clock
* aclk: cpu clock/2
* hclk: cpu clock/4
* pclk: cpu clock/8
*/
int cns3xxx_cpu_clock(void)
{
int cpu;
int cpu_sel;
int div_sel;
cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
return cpu;