Commit d91e4ea7 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc: Add support for CoreInt delivery of interrupts on MPIC



CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC.  This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent e60f57f5
...@@ -22,6 +22,14 @@ ...@@ -22,6 +22,14 @@
#define MPIC_GREG_FEATURE_1 0x00010 #define MPIC_GREG_FEATURE_1 0x00010
#define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
#define MPIC_GREG_GCONF_RESET 0x80000000 #define MPIC_GREG_GCONF_RESET 0x80000000
/* On the FSL mpic implementations the Mode field is expand to be
* 2 bits wide:
* 0b00 = pass through (interrupts routed to IRQ0)
* 0b01 = Mixed mode
* 0b10 = reserved
* 0b11 = External proxy / coreint
*/
#define MPIC_GREG_GCONF_COREINT 0x60000000
#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000
#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
...@@ -357,6 +365,8 @@ struct mpic ...@@ -357,6 +365,8 @@ struct mpic
#define MPIC_BROKEN_FRR_NIRQS 0x00000800 #define MPIC_BROKEN_FRR_NIRQS 0x00000800
/* Destination only supports a single CPU at a time */ /* Destination only supports a single CPU at a time */
#define MPIC_SINGLE_DEST_CPU 0x00001000 #define MPIC_SINGLE_DEST_CPU 0x00001000
/* Enable CoreInt delivery of interrupts */
#define MPIC_ENABLE_COREINT 0x00002000
/* MPIC HW modification ID */ /* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000 #define MPIC_REGSET_MASK 0xf0000000
...@@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq); ...@@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq);
extern unsigned int mpic_get_one_irq(struct mpic *mpic); extern unsigned int mpic_get_one_irq(struct mpic *mpic);
/* This one gets from the primary mpic */ /* This one gets from the primary mpic */
extern unsigned int mpic_get_irq(void); extern unsigned int mpic_get_irq(void);
/* This one gets from the primary mpic via CoreInt*/
extern unsigned int mpic_get_coreint_irq(void);
/* Fetch Machine Check interrupt from primary mpic */ /* Fetch Machine Check interrupt from primary mpic */
extern unsigned int mpic_get_mcirq(void); extern unsigned int mpic_get_mcirq(void);
......
...@@ -1170,6 +1170,12 @@ struct mpic * __init mpic_alloc(struct device_node *node, ...@@ -1170,6 +1170,12 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mb(); mb();
} }
/* CoreInt */
if (flags & MPIC_ENABLE_COREINT)
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_COREINT);
if (flags & MPIC_ENABLE_MCK) if (flags & MPIC_ENABLE_MCK)
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
...@@ -1525,6 +1531,34 @@ unsigned int mpic_get_irq(void) ...@@ -1525,6 +1531,34 @@ unsigned int mpic_get_irq(void)
return mpic_get_one_irq(mpic); return mpic_get_one_irq(mpic);
} }
unsigned int mpic_get_coreint_irq(void)
{
#ifdef CONFIG_BOOKE
struct mpic *mpic = mpic_primary;
u32 src;
BUG_ON(mpic == NULL);
src = mfspr(SPRN_EPR);
if (unlikely(src == mpic->spurious_vec)) {
if (mpic->flags & MPIC_SPV_EOI)
mpic_eoi(mpic);
return NO_IRQ;
}
if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
if (printk_ratelimit())
printk(KERN_WARNING "%s: Got protected source %d !\n",
mpic->name, (int)src);
return NO_IRQ;
}
return irq_linear_revmap(mpic->irqhost, src);
#else
return NO_IRQ;
#endif
}
unsigned int mpic_get_mcirq(void) unsigned int mpic_get_mcirq(void)
{ {
struct mpic *mpic = mpic_primary; struct mpic *mpic = mpic_primary;
......
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