Commit d6a4c0e5 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:

 - new drivers for:
        - Ingenic JZ4780 controller
        - APM X-Gene controller
        - Freescale RaidEngine device
        - Renesas USB Controller

  - remove device_alloc_chan_resources dummy handlers

  - sh driver cleanups for peri peri and related emmc and asoc patches
    as well

  - fixes and enhancements spread over the drivers

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (59 commits)
  dmaengine: dw: don't prompt for DW_DMAC_CORE
  dmaengine: shdmac: avoid unused variable warnings
  dmaengine: fix platform_no_drv_owner.cocci warnings
  dmaengine: pch_dma: fix memory leak on failure path in pch_dma_probe()
  dmaengine: at_xdmac: unlock spin lock before return
  dmaengine: xgene: devm_ioremap() returns NULL on error
  dmaengine: xgene: buffer overflow in xgene_dma_init_channels()
  dmaengine: usb-dmac: Fix dereferencing freed memory 'desc'
  dmaengine: sa11x0: report slave capabilities to upper layers
  dmaengine: vdma: Fix compilation warnings
  dmaengine: fsl_raid: statify fsl_re_chan_probe
  dmaengine: Driver support for FSL RaidEngine device.
  dmaengine: xgene_dma_init_ring_mngr() can be static
  Documentation: dma: Add documentation for the APM X-Gene SoC DMA device DTS binding
  arm64: dts: Add APM X-Gene SoC DMA device and DMA clock DTS nodes
  dmaengine: Add support for APM X-Gene SoC DMA engine driver
  dmaengine: usb-dmac: Add Renesas USB DMA Controller (USB-DMAC) driver
  dmaengine: renesas,usb-dmac: Add device tree bindings documentation
  dmaengine: edma: fixed wrongly initialized data parameter to the edma callback
  dmaengine: ste_dma40: fix implicit conversion
  ...
parents 474095e4 cdde0e61
Applied Micro X-Gene SoC DMA nodes
DMA nodes are defined to describe on-chip DMA interfaces in
APM X-Gene SoC.
Required properties for DMA interfaces:
- compatible: Should be "apm,xgene-dma".
- device_type: set to "dma".
- reg: Address and length of the register set for the device.
It contains the information of registers in the following order:
1st - DMA control and status register address space.
2nd - Descriptor ring control and status register address space.
3rd - Descriptor ring command register address space.
4th - Soc efuse register address space.
- interrupts: DMA has 5 interrupts sources. 1st interrupt is
DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
are completion interrupts for each DMA channels.
- clocks: Reference to the clock entry.
Optional properties:
- dma-coherent : Present if dma operations are coherent
Example:
dmaclk: dmaclk@1f27c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f27c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "dmaclk";
};
dma: dma@1f270000 {
compatible = "apm,xgene-storm-dma";
device_type = "dma";
reg = <0x0 0x1f270000 0x0 0x10000>,
<0x0 0x1f200000 0x0 0x10000>,
<0x0 0x1b008000 0x0 0x2000>,
<0x0 0x1054a000 0x0 0x100>;
interrupts = <0x0 0x82 0x4>,
<0x0 0xb8 0x4>,
<0x0 0xb9 0x4>,
<0x0 0xba 0x4>,
<0x0 0xbb 0x4>;
dma-coherent;
clocks = <&dmaclk 0>;
};
* Ingenic JZ4780 DMA Controller
Required properties:
- compatible: Should be "ingenic,jz4780-dma"
- reg: Should contain the DMA controller registers location and length.
- interrupts: Should contain the interrupt specifier of the DMA controller.
- interrupt-parent: Should be the phandle of the interrupt controller that
- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
DMA clients (see below).
Optional properties:
- ingenic,reserved-channels: Bitmask of channels to reserve for devices that
need a specific channel. These channels will only be assigned when explicitly
requested by a client. The primary use for this is channels 0 and 1, which
can be configured to have special behaviour for NAND/BCH when using
programmable firmware.
Example:
dma: dma@13420000 {
compatible = "ingenic,jz4780-dma";
reg = <0x13420000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <10>;
clocks = <&cgu JZ4780_CLK_PDMA>;
#dma-cells = <2>;
ingenic,reserved-channels = <0x3>;
};
DMA clients must use the format described in dma.txt, giving a phandle to the
DMA controller plus the following 2 integer cells:
1. Request type: The DMA request type for transfers to/from the device on
the allocated channel, as defined in the SoC documentation.
2. Channel: If set to 0xffffffff, any available channel will be allocated for
the client. Otherwise, the exact channel specified will be used. The channel
should be reserved on the DMA controller using the ingenic,reserved-channels
property.
Example:
uart0: serial@10030000 {
...
dmas = <&dma 0x14 0xffffffff
&dma 0x15 0xffffffff>;
dma-names = "tx", "rx";
...
};
......@@ -4,6 +4,7 @@ Required properties:
- compatible: must be one of the following:
* "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
* "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
* "qcom,bam-v1.7.0" for MSM8916
- reg: Address range for DMA registers
- interrupts: Should contain the one interrupt shared by all channels
- #dma-cells: must be <1>, the cell in the dmas property of the client device
......
* R-Car Audio DMAC peri peri Device Tree bindings
Required properties:
- compatible: should be "renesas,rcar-audmapp"
- #dma-cells: should be <1>, see "dmas" property below
Example:
audmapp: audio-dma-pp@0xec740000 {
compatible = "renesas,rcar-audmapp";
#dma-cells = <1>;
reg = <0 0xec740000 0 0x200>;
};
* DMA client
Required properties:
- dmas: a list of <[DMA multiplexer phandle] [SRS << 8 | DRS]> pairs.
where SRS/DRS are specified in the SoC manual.
It will be written into PDMACHCR as high 16-bit parts.
- dma-names: a list of DMA channel names, one per "dmas" entry
Example:
dmas = <&audmapp 0x2d00
&audmapp 0x3700>;
dma-names = "src0_ssiu0",
"dvc0_ssiu0";
* Renesas USB DMA Controller Device Tree bindings
Required Properties:
- compatible: must contain "renesas,usb-dmac"
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
- interrupt-names: one entry per channel, named "ch%u", where %u is the
channel number ranging from zero to the number of channels minus one.
- clocks: a list of phandle + clock-specifier pairs.
- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC
port connected to the DMA client.
- dma-channels: number of DMA channels
Example: R8A7790 (R-Car H2) USB-DMACs
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
#dma-cells = <1>;
dma-channels = <2>;
};
......@@ -5009,6 +5009,11 @@ W: http://industrypack.sourceforge.net
S: Maintained
F: drivers/ipack/
INGENIC JZ4780 DMA Driver
M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
S: Maintained
F: drivers/dma/dma-jz4780.c
INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
M: Mimi Zohar <zohar@linux.vnet.ibm.com>
M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com>
......
......@@ -754,12 +754,12 @@ static struct platform_device vcc_sdhi1 = {
};
/* SDHI0 */
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
static struct tmio_mmc_data sdhi0_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.cd_gpio = 167,
};
......@@ -796,12 +796,12 @@ static struct platform_device sdhi0_device = {
};
/* SDHI1 */
static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
static struct tmio_mmc_data sdhi1_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
/* Port72 cannot generate IRQs, will be used in polling mode. */
.cd_gpio = 72,
};
......
......@@ -201,12 +201,12 @@ static struct rcar_phy_platform_data usb_phy_platform_data __initdata =
/* SDHI */
static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
.dma_slave_tx = HPBDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = HPBDMA_SLAVE_SDHI0_RX,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
static struct tmio_mmc_data sdhi0_info __initdata = {
.chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SD_HIGHSPEED,
.ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
.flags = TMIO_MMC_HAS_IDLE_WAIT,
};
static struct resource sdhi0_resources[] __initdata = {
......@@ -683,7 +683,7 @@ static void __init bockw_init(void)
platform_device_register_resndata(
NULL, "sh_mobile_sdhi", 0,
sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
&sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
&sdhi0_info, sizeof(struct tmio_mmc_data));
}
/* for Audio */
......
......@@ -442,11 +442,11 @@ static struct platform_device vcc_sdhi2 = {
};
/* SDHI */
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
static struct tmio_mmc_data sdhi0_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.flags = TMIO_MMC_HAS_IDLE_WAIT,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
};
......@@ -484,13 +484,13 @@ static struct platform_device sdhi0_device = {
};
/* Micro SD */
static struct sh_mobile_sdhi_info sdhi2_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
static struct tmio_mmc_data sdhi2_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI2_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI2_RX,
.flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_USE_GPIO_CD |
TMIO_MMC_WRPROTECT_DISABLE,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
.cd_gpio = 13,
};
......
......@@ -122,11 +122,11 @@ static struct resource sdhi0_resources[] = {
},
};
static struct sh_mobile_sdhi_info sdhi0_platform_data = {
.dma_slave_tx = HPBDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = HPBDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
static struct tmio_mmc_data sdhi0_platform_data = {
.chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX,
.flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
.capabilities = MMC_CAP_SD_HIGHSPEED,
};
static struct platform_device sdhi0_device = {
......
......@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
......@@ -362,6 +363,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
dmaclk: dmaclk@1f27c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f27c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "dmaclk";
};
};
pcie0: pcie@1f2b0000 {
......@@ -684,5 +694,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
dma: dma@1f270000 {
compatible = "apm,xgene-storm-dma";
device_type = "dma";
reg = <0x0 0x1f270000 0x0 0x10000>,
<0x0 0x1f200000 0x0 0x10000>,
<0x0 0x1b008000 0x0 0x2000>,
<0x0 0x1054a000 0x0 0x100>;
interrupts = <0x0 0x82 0x4>,
<0x0 0xb8 0x4>,
<0x0 0xb9 0x4>,
<0x0 0xba 0x4>,
<0x0 0xbb 0x4>;
dma-coherent;
clocks = <&dmaclk 0>;
};
};
};
......@@ -17,6 +17,7 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/io.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
......@@ -243,10 +244,10 @@ static struct platform_device sh_mmcif_device = {
};
/* SDHI0 */
static struct sh_mobile_sdhi_info sdhi_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI_RX,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
static struct tmio_mmc_data sdhi_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX,
.capabilities = MMC_CAP_SD_HIGHSPEED,
};
static struct resource sdhi_resources[] = {
......
......@@ -18,6 +18,7 @@
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
#include <linux/mfd/tmio.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/regulator/fixed.h>
......@@ -447,8 +448,8 @@ static struct resource sdhi0_cn3_resources[] = {
},
};
static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sdhi0_cn3_data = {
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi0_cn3_device = {
......@@ -474,8 +475,8 @@ static struct resource sdhi1_cn7_resources[] = {
},
};
static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sdhi1_cn7_data = {
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi1_cn7_device = {
......
......@@ -601,12 +601,12 @@ static struct platform_device sdhi0_power = {
},
};
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
static struct tmio_mmc_data sdhi0_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
MMC_CAP_NEEDS_POLL,
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
.flags = TMIO_MMC_USE_GPIO_CD,
.cd_gpio = GPIO_PTY7,
};
......@@ -635,12 +635,12 @@ static struct platform_device sdhi0_device = {
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SDHI1 */
static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_caps = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
static struct tmio_mmc_data sdhi1_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
.capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
MMC_CAP_NEEDS_POLL,
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
.flags = TMIO_MMC_USE_GPIO_CD,
.cd_gpio = GPIO_PTW7,
};
......
......@@ -373,11 +373,11 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
},
};
static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sh7724_sdhi0_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.flags = TMIO_MMC_WRPROTECT_DISABLE,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device kfr2r09_sh_sdhi0_device = {
......
......@@ -15,6 +15,7 @@
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mtd/physmap.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/nand.h>
#include <linux/i2c.h>
#include <linux/regulator/fixed.h>
......@@ -408,10 +409,10 @@ static struct resource sdhi_cn9_resources[] = {
},
};
static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sh7724_sdhi_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi_cn9_device = {
......
......@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/regulator/fixed.h>
......@@ -468,10 +469,10 @@ static struct resource sdhi0_cn7_resources[] = {
},
};
static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sh7724_sdhi0_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi0_cn7_device = {
......@@ -497,10 +498,10 @@ static struct resource sdhi1_cn8_resources[] = {
},
};
static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_caps = MMC_CAP_SDIO_IRQ,
static struct tmio_mmc_data sh7724_sdhi1_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi1_cn8_device = {
......
......@@ -112,6 +112,17 @@ config FSL_DMA
EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
some Txxx and Bxxx parts.
config FSL_RAID
tristate "Freescale RAID engine Support"
depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
select DMA_ENGINE
select DMA_ENGINE_RAID
---help---
Enable support for Freescale RAID Engine. RAID Engine is
available on some QorIQ SoCs (like P5020/P5040). It has
the capability to offload memcpy, xor and pq computation
for raid5/6.
source "drivers/dma/hsu/Kconfig"
config MPC512X_DMA
......@@ -347,6 +358,16 @@ config DMA_JZ4740
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
config DMA_JZ4780
tristate "JZ4780 DMA support"
depends on MACH_JZ4780
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
This selects support for the DMA controller in Ingenic JZ4780 SoCs.
If you have a board based on such a SoC and wish to use DMA for
devices which can use the DMA controller, say Y or M here.
config K3_DMA
tristate "Hisilicon K3 DMA support"
depends on ARCH_HI3xxx
......@@ -414,6 +435,14 @@ config IMG_MDC_DMA
help
Enable support for the IMG multi-threaded DMA controller (MDC).
config XGENE_DMA
tristate "APM X-Gene DMA support"
select DMA_ENGINE
select DMA_ENGINE_RAID
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
help
Enable support for the APM X-Gene SoC DMA engine.
config DMA_ENGINE
bool
......
......@@ -41,9 +41,11 @@ obj-$(CONFIG_DMA_OMAP) += omap-dma.o
obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_K3_DMA) += k3dma.o
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
obj-y += xilinx/
......@@ -51,3 +53,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
......@@ -15,10 +15,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* The full GNU General Public License is in this distribution in the file
* called COPYING.
*
......@@ -1195,11 +1191,6 @@ static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
/*
* The DMA ENGINE API
*/
static int pl08x_alloc_chan_resources(struct dma_chan *chan)