Commit ccaec3ec authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] versatile: remove IRQ mask definitions



These definitions are unused and serve no purpose with genirq.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 7ef4de17
......@@ -60,39 +60,6 @@
#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
#define IRQ_VIC_END (IRQ_VIC_START + 31)
#define IRQMASK_WDOGINT INTMASK_WDOGINT
#define IRQMASK_SOFTINT INTMASK_SOFTINT
#define IRQMASK_COMMRx INTMASK_COMMRx
#define IRQMASK_COMMTx INTMASK_COMMTx
#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
#define IRQMASK_RTCINT INTMASK_RTCINT
#define IRQMASK_SSPINT INTMASK_SSPINT
#define IRQMASK_UARTINT0 INTMASK_UARTINT0
#define IRQMASK_UARTINT1 INTMASK_UARTINT1
#define IRQMASK_UARTINT2 INTMASK_UARTINT2
#define IRQMASK_SCIINT INTMASK_SCIINT
#define IRQMASK_CLCDINT INTMASK_CLCDINT
#define IRQMASK_DMAINT INTMASK_DMAINT
#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
#define IRQMASK_MBXINT INTMASK_MBXINT
#define IRQMASK_GNDINT INTMASK_GNDINT
#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
/*
* FIQ interrupts definitions are the same as the INT definitions.
*/
......@@ -130,39 +97,6 @@
#define FIQ_VICSOURCE31 INT_VICSOURCE31
#define FIQMASK_WDOGINT INTMASK_WDOGINT
#define FIQMASK_SOFTINT INTMASK_SOFTINT
#define FIQMASK_COMMRx INTMASK_COMMRx
#define FIQMASK_COMMTx INTMASK_COMMTx
#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
#define FIQMASK_RTCINT INTMASK_RTCINT
#define FIQMASK_SSPINT INTMASK_SSPINT
#define FIQMASK_UARTINT0 INTMASK_UARTINT0
#define FIQMASK_UARTINT1 INTMASK_UARTINT1
#define FIQMASK_UARTINT2 INTMASK_UARTINT2
#define FIQMASK_SCIINT INTMASK_SCIINT
#define FIQMASK_CLCDINT INTMASK_CLCDINT
#define FIQMASK_DMAINT INTMASK_DMAINT
#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
#define FIQMASK_MBXINT INTMASK_MBXINT
#define FIQMASK_GNDINT INTMASK_GNDINT
#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
/*
* Secondary interrupt controller
*/
......@@ -188,24 +122,4 @@
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
#define IRQ_SIC_END 63
#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
#define SIC_IRQMASK_DoC SIC_INTMASK_DoC
#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
#define SIC_IRQMASK_AACI SIC_INTMASK_AACI
#define SIC_IRQMASK_ETH SIC_INTMASK_ETH
#define SIC_IRQMASK_USB SIC_INTMASK_USB
#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
#define NR_IRQS 64
......@@ -347,44 +347,6 @@
#define INT_VICSOURCE30 30 /* PCI 3 */
#define INT_VICSOURCE31 31 /* SIC source */
/*
* Interrupt bit positions
*
*/
#define INTMASK_WDOGINT (1 << INT_WDOGINT)
#define INTMASK_SOFTINT (1 << INT_SOFTINT)
#define INTMASK_COMMRx (1 << INT_COMMRx)
#define INTMASK_COMMTx (1 << INT_COMMTx)
#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
#define INTMASK_RTCINT (1 << INT_RTCINT)
#define INTMASK_SSPINT (1 << INT_SSPINT)
#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
#define INTMASK_SCIINT (1 << INT_SCIINT)
#define INTMASK_CLCDINT (1 << INT_CLCDINT)
#define INTMASK_DMAINT (1 << INT_DMAINT)
#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
#define INTMASK_MBXINT (1 << INT_MBXINT)
#define INTMASK_GNDINT (1 << INT_GNDINT)
#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
#define VERSATILE_SC_VALID_INT 0x003FFFFF
#define MAXIRQNUM 31
......@@ -417,26 +379,6 @@
#define SIC_INT_PCI3 30
#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
#define SIC_INTMASK_USB (1 << SIC_INT_USB)
#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
/*
* Clean base - dummy
*
......
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