Commit cb33c412 authored by Senthil Balasubramanian's avatar Senthil Balasubramanian Committed by John W. Linville

ath9k: INI update for Atheros AR9280 and AR9285 chipset.

Signed-off-by: default avatarSenthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 92d6128e
......@@ -2121,6 +2121,7 @@ void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan)
static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
struct ath9k_channel *chan)
{
#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
struct modal_eep_header *pModal;
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
......@@ -2163,9 +2164,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
if ((eep->baseEepHeader.version &
AR5416_EEP_VER_MINOR_MASK) >=
AR5416_EEP_MINOR_VER_3) {
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
txRxAttenLocal = pModal->txRxAttenCh[i];
if (AR_SREV_9280_10_OR_LATER(ah)) {
REG_RMW_FIELD(ah,
......@@ -2332,8 +2331,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
pModal->thresh62);
}
if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
AR5416_EEP_MINOR_VER_2) {
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
AR_PHY_TX_END_DATA_START,
pModal->txFrameToDataStart);
......@@ -2341,15 +2339,29 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
pModal->txFrameToPaOn);
}
if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
AR5416_EEP_MINOR_VER_3) {
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
if (IS_CHAN_HT40(chan))
REG_RMW_FIELD(ah, AR_PHY_SETTLING,
AR_PHY_SETTLING_SWITCH,
pModal->swSettleHt40);
}
if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
if (IS_CHAN_HT20(chan))
REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
eep->baseEepHeader.dacLpMode);
else if (eep->baseEepHeader.dacHiPwrMode_5G)
REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
else
REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
eep->baseEepHeader.dacLpMode);
REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
pModal->miscBits >> 2);
}
return true;
#undef AR5416_VER_MASK
}
static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah,
......@@ -2739,6 +2751,7 @@ static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
enum eeprom_param param)
{
#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
struct ath_hal_5416 *ahp = AH5416(ah);
struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
struct modal_eep_header *pModal = eep->modalHeader;
......@@ -2774,7 +2787,7 @@ static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
case EEP_DB_2:
return pModal[1].db;
case EEP_MINOR_REV:
return pBase->version & AR5416_EEP_VER_MINOR_MASK;
return AR5416_VER_MASK;
case EEP_TX_MASK:
return pBase->txMask;
case EEP_RX_MASK:
......@@ -2783,10 +2796,15 @@ static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
return pBase->rxGainType;
case EEP_TXGAIN_TYPE:
return pBase->txGainType;
case EEP_DAC_HPWR_5G:
if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
return pBase->dacHiPwrMode_5G;
else
return 0;
default:
return 0;
}
#undef AR5416_VER_MASK
}
static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = {
......
......@@ -3272,7 +3272,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
pCap->num_mr_retries = 4;
pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
if (AR_SREV_9280_10_OR_LATER(ah))
if (AR_SREV_9285_10_OR_LATER(ah))
pCap->num_gpio_pins = AR9285_NUM_GPIO;
else if (AR_SREV_9280_10_OR_LATER(ah))
pCap->num_gpio_pins = AR928X_NUM_GPIO;
else
pCap->num_gpio_pins = AR_NUM_GPIO;
......@@ -3517,17 +3519,18 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
{
#define MS_REG_READ(x, y) \
(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
if (gpio >= ah->ah_caps.num_gpio_pins)
return 0xffffffff;
if (AR_SREV_9280_10_OR_LATER(ah)) {
return (MS
(REG_READ(ah, AR_GPIO_IN_OUT),
AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
} else {
return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
AR_GPIO_BIT(gpio)) != 0;
}
if (AR_SREV_9285_10_OR_LATER(ah))
return MS_REG_READ(AR9285, gpio) != 0;
else if (AR_SREV_9280_10_OR_LATER(ah))
return MS_REG_READ(AR928X, gpio) != 0;
else
return MS_REG_READ(AR, gpio) != 0;
}
void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
......
......@@ -426,6 +426,7 @@ struct ar5416Stats {
#define AR5416_EEP_MINOR_VER_16 0x10
#define AR5416_EEP_MINOR_VER_17 0x11
#define AR5416_EEP_MINOR_VER_19 0x13
#define AR5416_EEP_MINOR_VER_20 0x14
#define AR5416_NUM_5G_CAL_PIERS 8
#define AR5416_NUM_2G_CAL_PIERS 4
......@@ -488,6 +489,7 @@ enum eeprom_param {
EEP_RX_MASK,
EEP_RXGAIN_TYPE,
EEP_TXGAIN_TYPE,
EEP_DAC_HPWR_5G,
};
enum ar5416_rates {
......@@ -526,9 +528,13 @@ struct base_eep_header {
u8 pwdclkind;
u8 futureBase_1[2];
u8 rxGainType;
u8 futureBase_2[3];
u8 dacHiPwrMode_5G;
u8 futureBase_2;
u8 dacLpMode;
u8 txGainType;
u8 futureBase_3[25];
u8 rcChainMask;
u8 desiredScaleCCK;
u8 futureBase_3[23];
} __packed;
struct base_eep_header_4k {
......@@ -595,7 +601,7 @@ struct modal_eep_header {
force_xpaon:1,
local_bias:1,
femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
u8 futureModalar9280;
u8 miscBits;
u16 xpaBiasLvlFreq[3];
u8 futureModal[6];
......
This diff is collapsed.
......@@ -875,12 +875,15 @@ enum {
#define AR_NUM_GPIO 14
#define AR928X_NUM_GPIO 10
#define AR9285_NUM_GPIO 12
#define AR_GPIO_IN_OUT 0x4048
#define AR_GPIO_IN_VAL 0x0FFFC000
#define AR_GPIO_IN_VAL_S 14
#define AR928X_GPIO_IN_VAL 0x000FFC00
#define AR928X_GPIO_IN_VAL_S 10
#define AR9285_GPIO_IN_VAL 0x00FFF000
#define AR9285_GPIO_IN_VAL_S 12
#define AR_GPIO_OE_OUT 0x404c
#define AR_GPIO_OE_OUT_DRV 0x3
......@@ -1021,6 +1024,10 @@ enum {
#define AR_AN_RF5G1_CH1_DB5 0x00380000
#define AR_AN_RF5G1_CH1_DB5_S 19
#define AR_AN_TOP1 0x7890
#define AR_AN_TOP1_DACIPMODE 0x00040000
#define AR_AN_TOP1_DACIPMODE_S 18
#define AR_AN_TOP2 0x7894
#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
#define AR_AN_TOP2_XPABIAS_LVL_S 30
......
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