Commit c819e2cf authored by Jiri Olsa's avatar Jiri Olsa Committed by Arnaldo Carvalho de Melo
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tools build: Add new build support

Adding new build framework into 'tools/build' to be used by tools.

There's no change for actual building at this point, it comes in the
next patches.

The idea and more details are explained in the
'tools/build/Documentation/Build.txt' file.

I adopted everything from the kernel build system, with some changes to
allow for multiple binaries build definitions.

While the kernel's build output is single image (forget modules) we need
to be able to build several binaries/libraries.

The basic idea is that sser provides 'Build' files with objects
definitions like:

  perf-y += a.o
  perf-y += b.o
  libperf-y += c.o
  libperf-y += d.o

and the build framework outputs files:

  perf-in.o    # a.o, b.o compiled in
  libperf-in.o # c.o, d.o compiled in
Signed-off-by: default avatarJiri Olsa <>
Tested-by: default avatarSukadev Bhattiprolu <>
Tested-by: default avatarWill Deacon <>
Cc: Alexis Berlemont <>
Cc: Borislav Petkov <>
Cc: Corey Ashford <>
Cc: David Ahern <>
Cc: Frederic Weisbecker <>
Cc: Namhyung Kim <>
Cc: Paul Mackerras <>
Cc: Peter Zijlstra <>
Cc: Stephane Eranian <>

Signed-off-by: default avatarArnaldo Carvalho de Melo <>
parent 39f57043
# build: Generic definitions
# Lots of this code have been borrowed or heavily inspired from parts
# of kbuild code, which is not credited, but mostly developed by:
# Copyright (C) Sam Ravnborg <>, 2015
# Copyright (C) Linus Torvalds <>, 2015
# Convenient variables
comma := ,
squote := '
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
dot-target = $(dir $@).$(notdir $@)
# filename of target with directory and extension stripped
basetarget = $(basename $(notdir $@))
# The temporary file to save gcc -MD generated dependencies must not
# contain a comma
depfile = $(subst $(comma),_,$(dot-target).d)
# Check if both arguments has same arguments. Result is empty string if equal.
arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
$(filter-out $(cmd_$@), $(cmd_$(1))) )
# Escape single quote for use in echo statements
escsq = $(subst $(squote),'\$(squote)',$1)
# Echo command
# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
echo-cmd = $(if $($(quiet)cmd_$(1)),\
echo ' $(call escsq,$($(quiet)cmd_$(1)))';)
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
# (needed for make)
# Replace >#< with >\#< to avoid starting a comment in the .cmd file
# (needed for make)
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
# (needed for the shell)
make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
# Find any prerequisites that is newer than target or that does not exist.
# PHONY targets skipped in both cases.
any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
# if_changed_dep - execute command if any prerequisite is newer than
# target, or command line has changed and update
# dependencies in the cmd file
if_changed_dep = $(if $(strip $(any-prereq) $(arg-check)), \
@set -e; \
$(echo-cmd) $(cmd_$(1)); \
cat $(depfile) > $(dot-target).cmd; \
printf '%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd)
# if_changed - execute command if any prerequisite is newer than
# target, or command line has changed
if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
@set -e; \
$(echo-cmd) $(cmd_$(1)); \
printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
# C flags to be used in rule definitions, includes:
# - depfile generation
# - global $(CFLAGS)
# - per target C flags
# - per object C flags
# - BUILD_STR macro to allow '-D"$(variable)"' constructs
c_flags = -Wp,-MD,$(depfile),-MT,$@ $(CFLAGS) -D"BUILD_STR(s)=\#s" $(CFLAGS_$(basetarget).o) $(CFLAGS_$(obj))
Build Framework
The perf build framework was adopted from the kernel build system, hence the
idea and the way how objects are built is the same.
Basically the user provides set of 'Build' files that list objects and
directories to nest for specific target to be build.
Unlike the kernel we don't have a single build object 'obj-y' list that where
we setup source objects, but we support more. This allows one 'Build' file to
carry a sources list for multiple build objects.
a) Build framework makefiles
The build framework consists of 2 Makefiles:
While the 'Build.include' file contains just some generic definitions, the
'' file is the makefile used from the outside. It's
interface/usage is following:
$ make -f tools/build/Makefile srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
KSRC - is the path to kernel sources
DIR - is the path to the project to be built
OBJECT - is the name of the build object
When succefully finished the $(DIR) directory contains the final object file
called $(OBJECT)-in.o:
$ ls $(DIR)/$(OBJECT)-in.o
which includes all compiled sources described in 'Build' makefiles.
a) Build makefiles
The user supplies 'Build' makefiles that contains a objects list, and connects
the build to nested directories.
Assume we have the following project structure:
Out of which you build the 'ex' binary ' and the 'libex.a' library:
'ex' - consists of 'a.o', 'b.o' and libex.a
'libex.a' - consists of 'c.o', 'd.o', 'e.o' and 'f.o'
The build framework does not create the 'ex' and 'libex.a' binaries for you, it
only prepares proper objects to be compiled and grouped together.
To follow the above example, the user provides following 'Build' files:
ex-y += a.o
ex-y += b.o
libex-y += c.o
libex-y += d.o
libex-y += arch/
libex-y += e.o
libex-y += f.o
and runs:
$ make -f tools/build/ dir=. obj=ex
$ make -f tools/build/ dir=. obj=libex
which creates the following objects:
that contain request objects names in Build files.
It's only a matter of 2 single commands to create the final binaries:
$ ar rcs libex.a libex-in.o
$ gcc -o ex ex-in.o libex.a
You can check the 'ex' example in 'tools/build/tests/ex' for more details.
b) Rules
The build framework provides standard compilation rules to handle .S and .c
It's possible to include special rule if needed (like we do for flex or bison
code generation).
It's possible to alter the standard object C flags in the following way:
CFLAGS_perf.o += '...' - alters CFLAGS for perf.o object
CFLAGS_gtk += '...' - alters CFLAGS for gtk build object
This C flags changes has the scope of the Build makefile they are defined in.
d) Dependencies
For each built object file 'a.o' the '.a.cmd' is created and holds:
- Command line used to built that object
(for each object)
- Dependency rules generated by 'gcc -Wp,-MD,...'
(for compiled object)
All existing '.cmd' files are included in the Build process to follow properly
the dependencies and trigger a rebuild when necessary.
e) Single rules
It's possible to build single object file by choice, like:
$ make util/map.o # objects
$ make util/map.i # preprocessor
$ make util/map.s # assembly
# Main build makefile.
# Lots of this code have been borrowed or heavily inspired from parts
# of kbuild code, which is not credited, but mostly developed by:
# Copyright (C) Sam Ravnborg <>, 2015
# Copyright (C) Linus Torvalds <>, 2015
PHONY := __build
ifeq ($(V),1)
quiet =
build-dir := $(srctree)/tools/build
# Generic definitions
include $(build-dir)/Build.include
# Init all relevant variables used in build files so
# 1) they have correct type
# 2) they do not inherit any value from the environment
subdir-y :=
obj-y :=
subdir-y :=
subdir-obj-y :=
# Build definitions
build-file := $(dir)/Build
include $(build-file)
# Compile command
quiet_cmd_cc_o_c = CC $@
cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
# Link agregate command
# If there's nothing to link, create empty $@ object.
quiet_cmd_ld_multi = LD $@
cmd_ld_multi = $(if $(strip $(obj-y)),\
$(LD) -r -o $@ $(obj-y),rm -f $@; $(AR) rcs $@)
# Build rules
$(OUTPUT)%.o: %.c FORCE
$(call if_changed_dep,cc_o_c)
$(call if_changed_dep,cc_o_c)
# Gather build data:
# obj-y - list of build objects
# subdir-y - list of directories to nest
# subdir-obj-y - list of directories objects 'dir/$(obj)-in.o'
obj-y := $($(obj)-y)
subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
obj-y := $(patsubst %/, %/$(obj)-in.o, $(obj-y))
subdir-obj-y := $(filter %/$(obj)-in.o, $(obj-y))
# '$(OUTPUT)/dir' prefix to all objects
prefix := $(subst ./,,$(OUTPUT)$(dir)/)
obj-y := $(addprefix $(prefix),$(obj-y))
subdir-obj-y := $(addprefix $(prefix),$(subdir-obj-y))
# Final '$(obj)-in.o' object
in-target := $(prefix)$(obj)-in.o
PHONY += $(subdir-y)
@$(MAKE) -f $(build-dir)/ dir=$(dir)/$@ obj=$(obj)
$(sort $(subdir-obj-y)): $(subdir-y) ;
$(in-target): $(obj-y) FORCE
$(call rule_mkdir)
$(call if_changed,ld_multi)
__build: $(in-target)
# Include all cmd files to get all the dependency rules
# for all objects included
targets := $(wildcard $(sort $(obj-y) $(in-target)))
cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
ifneq ($(cmd_files),)
include $(cmd_files)
ex-y += ex.o
ex-y += a.o
ex-y += b.o
ex-y += empty/
libex-y += c.o
libex-y += d.o
libex-y += arch/
export srctree := ../../../..
export CC := gcc
export LD := ld
export AR := ar
build := -f $(srctree)/tools/build/ dir=. obj
ex: ex-in.o libex-in.o
gcc -o $@ $^
ex.%: FORCE
make -f $(srctree)/tools/build/ dir=. $@
ex-in.o: FORCE
make $(build)=ex
libex-in.o: FORCE
make $(build)=libex
find . -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete
rm -f ex ex.i ex.s
int a(void)
return 0;
libex-y += e.o
libex-y += f.o
int e(void)
return 0;
int f(void)
return 0;
int b(void)
return 0;
int c(void)
return 0;
int d(void)
return 0;
int a(void);
int b(void);
int c(void);
int d(void);
int e(void);
int f(void);
int main(void)
return 0;
function test_ex {
make -C ex V=1 clean > ex.out 2>&1
make -C ex V=1 >> ex.out 2>&1
if [ ! -x ./ex/ex ]; then
exit -1
make -C ex V=1 clean > /dev/null 2>&1
rm -f ex.out
function test_ex_suffix {
make -C ex V=1 clean > ex.out 2>&1
# use -rR to disable make's builtin rules
make -rR -C ex V=1 ex.o >> ex.out 2>&1
make -rR -C ex V=1 ex.i >> ex.out 2>&1
make -rR -C ex V=1 ex.s >> ex.out 2>&1
if [ -x ./ex/ex ]; then
exit -1
if [ ! -f ./ex/ex.o -o ! -f ./ex/ex.i -o ! -f ./ex/ex.s ]; then
exit -1
make -C ex V=1 clean > /dev/null 2>&1
rm -f ex.out
echo -n Testing..
echo OK
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