Commit c747f97c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm amd fixes from Dave Airlie:
 "Been pretty quiet.

  This is an amdgpu fixes pull from AMD, a bunch of powerplay stability
  fixes, race fix, hibernate fix, and a possible circular locking fix"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (21 commits)
  drm/amdgpu: fix issue with overlapping userptrs
  drm/radeon: hold reference to fences in radeon_sa_bo_new
  drm/amdgpu: remove unnecessary forward declaration
  drm/amdgpu: hold reference to fences in amdgpu_sa_bo_new (v2)
  drm/amdgpu: fix s4 resume
  drm/amdgpu/cz: plumb pg flags through to powerplay
  drm/amdgpu/tonga: plumb pg flags through to powerplay
  drma/dmgpu: move cg and pg flags into shared headers
  drm/amdgpu: remove unused cg defines
  drm/amdgpu: add a cgs interface to fetch cg and pg flags
  drm/amd/powerplay/tonga: disable vce pg
  drm/amd/powerplay/tonga: disable uvd pg
  drm/amd/powerplay/cz: disable vce pg
  drm/amd/powerplay/cz: disable uvd pg
  drm/amdgpu: be consistent with uvd cg flags
  drm/amdgpu: clean up vce pg flags for cz/st
  drm/amdgpu: handle vce pg flags properly
  drm/amdgpu: handle uvd pg flags properly
  drm/amdgpu/dpm/ci: switch over to the common pcie caps interface
  drm/amdgpu/cik: don't mess with aspm if gpu is root bus
  ...
parents df8c2723 c92a428f
......@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern int amdgpu_enable_semaphores;
extern int amdgpu_powerplay;
extern unsigned amdgpu_pcie_gen_cap;
extern unsigned amdgpu_pcie_lane_cap;
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
......@@ -132,47 +134,6 @@ extern int amdgpu_powerplay;
#define AMDGPU_RESET_VCE (1 << 13)
#define AMDGPU_RESET_VCE1 (1 << 14)
/* CG block flags */
#define AMDGPU_CG_BLOCK_GFX (1 << 0)
#define AMDGPU_CG_BLOCK_MC (1 << 1)
#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
#define AMDGPU_CG_BLOCK_UVD (1 << 3)
#define AMDGPU_CG_BLOCK_VCE (1 << 4)
#define AMDGPU_CG_BLOCK_HDP (1 << 5)
#define AMDGPU_CG_BLOCK_BIF (1 << 6)
/* CG flags */
#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
/* PG flags */
#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
#define AMDGPU_PG_SUPPORT_CP (1 << 5)
#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
/* GFX current status */
#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
#define AMDGPU_GFX_SAFE_MODE 0x00000001L
......@@ -606,8 +567,6 @@ struct amdgpu_sa_manager {
uint32_t align;
};
struct amdgpu_sa_bo;
/* sub-allocation buffer */
struct amdgpu_sa_bo {
struct list_head olist;
......@@ -2360,6 +2319,8 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
uint32_t flags);
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
unsigned long end);
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem);
......
......@@ -795,6 +795,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
case CGS_SYSTEM_INFO_PCIE_MLW:
sys_info->value = adev->pm.pcie_mlw_mask;
break;
case CGS_SYSTEM_INFO_CG_FLAGS:
sys_info->value = adev->cg_flags;
break;
case CGS_SYSTEM_INFO_PG_FLAGS:
sys_info->value = adev->pg_flags;
break;
default:
return -ENODEV;
}
......
......@@ -1795,15 +1795,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
}
/* post card */
amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (!amdgpu_card_posted(adev))
amdgpu_atom_asic_init(adev->mode_info.atom_context);
r = amdgpu_resume(adev);
if (r)
DRM_ERROR("amdgpu_resume failed (%d).\n", r);
amdgpu_fence_driver_resume(adev);
r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
if (resume) {
r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
r = amdgpu_late_init(adev);
if (r)
......@@ -1933,80 +1938,97 @@ retry:
return r;
}
#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
void amdgpu_get_pcie_info(struct amdgpu_device *adev)
{
u32 mask;
int ret;
if (pci_is_root_bus(adev->pdev->bus))
return;
if (amdgpu_pcie_gen_cap)
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
if (amdgpu_pcie_gen2 == 0)
return;
if (amdgpu_pcie_lane_cap)
adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
if (adev->flags & AMD_IS_APU)
/* covers APUs as well */
if (pci_is_root_bus(adev->pdev->bus)) {
if (adev->pm.pcie_gen_mask == 0)
adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
if (adev->pm.pcie_mlw_mask == 0)
adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
return;
}
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
if (!ret) {
adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
if (mask & DRM_PCIE_SPEED_25)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
if (mask & DRM_PCIE_SPEED_50)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
if (mask & DRM_PCIE_SPEED_80)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
}
ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
if (!ret) {
switch (mask) {
case 32:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 16:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 12:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 8:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 4:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 2:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 1:
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
break;
default:
break;
if (adev->pm.pcie_gen_mask == 0) {
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
if (!ret) {
adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
if (mask & DRM_PCIE_SPEED_25)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
if (mask & DRM_PCIE_SPEED_50)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
if (mask & DRM_PCIE_SPEED_80)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
} else {
adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
}
}
if (adev->pm.pcie_mlw_mask == 0) {
ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
if (!ret) {
switch (mask) {
case 32:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 16:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 12:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 8:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 4:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 2:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 1:
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
break;
default:
break;
}
} else {
adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
}
}
}
......
......@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32;
int amdgpu_sched_hw_submission = 2;
int amdgpu_enable_semaphores = 0;
int amdgpu_powerplay = -1;
unsigned amdgpu_pcie_gen_cap = 0;
unsigned amdgpu_pcie_lane_cap = 0;
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
......@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
module_param_named(powerplay, amdgpu_powerplay, int, 0444);
#endif
MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
static struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_CIK
/* Kaveri */
......
......@@ -142,7 +142,8 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
list_for_each_entry(bo, &node->bos, mn_list) {
if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)
if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start,
end))
continue;
r = amdgpu_bo_reserve(bo, true);
......
......@@ -354,12 +354,15 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
if (fences[i])
fences[count++] = fences[i];
fences[count++] = fence_get(fences[i]);
if (count) {
spin_unlock(&sa_manager->wq.lock);
t = fence_wait_any_timeout(fences, count, false,
MAX_SCHEDULE_TIMEOUT);
for (i = 0; i < count; ++i)
fence_put(fences[i]);
r = (t > 0) ? 0 : t;
spin_lock(&sa_manager->wq.lock);
} else {
......
......@@ -783,6 +783,25 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
return !!gtt->userptr;
}
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
unsigned long end)
{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
unsigned long size;
if (gtt == NULL)
return false;
if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
return false;
size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
if (gtt->userptr > end || gtt->userptr + size <= start)
return false;
return true;
}
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
......
......@@ -31,6 +31,7 @@
#include "ci_dpm.h"
#include "gfx_v7_0.h"
#include "atom.h"
#include "amd_pcie.h"
#include <linux/seq_file.h>
#include "smu/smu_7_0_1_d.h"
......@@ -5835,18 +5836,16 @@ static int ci_dpm_init(struct amdgpu_device *adev)
u8 frev, crev;
struct ci_power_info *pi;
int ret;
u32 mask;
pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
if (pi == NULL)
return -ENOMEM;
adev->pm.dpm.priv = pi;
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
if (ret)
pi->sys_pcie_mask = 0;
else
pi->sys_pcie_mask = mask;
pi->sys_pcie_mask =
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
......
......@@ -1762,6 +1762,9 @@ static void cik_program_aspm(struct amdgpu_device *adev)
if (amdgpu_aspm == 0)
return;
if (pci_is_root_bus(adev->pdev->bus))
return;
/* XXX double check APUs */
if (adev->flags & AMD_IS_APU)
return;
......@@ -2332,72 +2335,72 @@ static int cik_common_early_init(void *handle)
switch (adev->asic_type) {
case CHIP_BONAIRE:
adev->cg_flags =
AMDGPU_CG_SUPPORT_GFX_MGCG |
AMDGPU_CG_SUPPORT_GFX_MGLS |
/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
AMDGPU_CG_SUPPORT_GFX_CGLS |
AMDGPU_CG_SUPPORT_GFX_CGTS |
AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
AMDGPU_CG_SUPPORT_GFX_CP_LS |
AMDGPU_CG_SUPPORT_MC_LS |
AMDGPU_CG_SUPPORT_MC_MGCG |
AMDGPU_CG_SUPPORT_SDMA_MGCG |
AMDGPU_CG_SUPPORT_SDMA_LS |
AMDGPU_CG_SUPPORT_BIF_LS |
AMDGPU_CG_SUPPORT_VCE_MGCG |
AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_HDP_LS |
AMDGPU_CG_SUPPORT_HDP_MGCG;
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
/*AMD_CG_SUPPORT_GFX_CGCG |*/
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGTS |
AMD_CG_SUPPORT_GFX_CGTS_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_VCE_MGCG |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14;
break;
case CHIP_HAWAII:
adev->cg_flags =
AMDGPU_CG_SUPPORT_GFX_MGCG |
AMDGPU_CG_SUPPORT_GFX_MGLS |
/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
AMDGPU_CG_SUPPORT_GFX_CGLS |
AMDGPU_CG_SUPPORT_GFX_CGTS |
AMDGPU_CG_SUPPORT_GFX_CP_LS |
AMDGPU_CG_SUPPORT_MC_LS |
AMDGPU_CG_SUPPORT_MC_MGCG |
AMDGPU_CG_SUPPORT_SDMA_MGCG |
AMDGPU_CG_SUPPORT_SDMA_LS |
AMDGPU_CG_SUPPORT_BIF_LS |
AMDGPU_CG_SUPPORT_VCE_MGCG |
AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_HDP_LS |
AMDGPU_CG_SUPPORT_HDP_MGCG;
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
/*AMD_CG_SUPPORT_GFX_CGCG |*/
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGTS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_VCE_MGCG |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = 0x28;
break;
case CHIP_KAVERI:
adev->cg_flags =
AMDGPU_CG_SUPPORT_GFX_MGCG |
AMDGPU_CG_SUPPORT_GFX_MGLS |
/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
AMDGPU_CG_SUPPORT_GFX_CGLS |
AMDGPU_CG_SUPPORT_GFX_CGTS |
AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
AMDGPU_CG_SUPPORT_GFX_CP_LS |
AMDGPU_CG_SUPPORT_SDMA_MGCG |
AMDGPU_CG_SUPPORT_SDMA_LS |
AMDGPU_CG_SUPPORT_BIF_LS |
AMDGPU_CG_SUPPORT_VCE_MGCG |
AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_HDP_LS |
AMDGPU_CG_SUPPORT_HDP_MGCG;
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
/*AMD_CG_SUPPORT_GFX_CGCG |*/
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGTS |
AMD_CG_SUPPORT_GFX_CGTS_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_VCE_MGCG |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags =
/*AMDGPU_PG_SUPPORT_GFX_PG |
AMDGPU_PG_SUPPORT_GFX_SMG |
AMDGPU_PG_SUPPORT_GFX_DMG |*/
AMDGPU_PG_SUPPORT_UVD |
/*AMDGPU_PG_SUPPORT_VCE |
AMDGPU_PG_SUPPORT_CP |
AMDGPU_PG_SUPPORT_GDS |
AMDGPU_PG_SUPPORT_RLC_SMU_HS |
AMDGPU_PG_SUPPORT_ACP |
AMDGPU_PG_SUPPORT_SAMU |*/
/*AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_GFX_DMG |*/
AMD_PG_SUPPORT_UVD |
/*AMD_PG_SUPPORT_VCE |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_GDS |
AMD_PG_SUPPORT_RLC_SMU_HS |
AMD_PG_SUPPORT_ACP |
AMD_PG_SUPPORT_SAMU |*/
0;
if (adev->pdev->device == 0x1312 ||
adev->pdev->device == 0x1316 ||
......@@ -2409,29 +2412,29 @@ static int cik_common_early_init(void *handle)
case CHIP_KABINI:
case CHIP_MULLINS:
adev->cg_flags =
AMDGPU_CG_SUPPORT_GFX_MGCG |
AMDGPU_CG_SUPPORT_GFX_MGLS |
/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
AMDGPU_CG_SUPPORT_GFX_CGLS |
AMDGPU_CG_SUPPORT_GFX_CGTS |
AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
AMDGPU_CG_SUPPORT_GFX_CP_LS |
AMDGPU_CG_SUPPORT_SDMA_MGCG |
AMDGPU_CG_SUPPORT_SDMA_LS |
AMDGPU_CG_SUPPORT_BIF_LS |
AMDGPU_CG_SUPPORT_VCE_MGCG |
AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_HDP_LS |
AMDGPU_CG_SUPPORT_HDP_MGCG;
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
/*AMD_CG_SUPPORT_GFX_CGCG |*/
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGTS |
AMD_CG_SUPPORT_GFX_CGTS_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_VCE_MGCG |
AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_MGCG;
adev->pg_flags =
/*AMDGPU_PG_SUPPORT_GFX_PG |
AMDGPU_PG_SUPPORT_GFX_SMG | */
AMDGPU_PG_SUPPORT_UVD |
/*AMDGPU_PG_SUPPORT_VCE |
AMDGPU_PG_SUPPORT_CP |
AMDGPU_PG_SUPPORT_GDS |
AMDGPU_PG_SUPPORT_RLC_SMU_HS |
AMDGPU_PG_SUPPORT_SAMU |*/
/*AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_GFX_SMG | */
AMD_PG_SUPPORT_UVD |
/*AMD_PG_SUPPORT_VCE |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_GDS |
AMD_PG_SUPPORT_RLC_SMU_HS |
AMD_PG_SUPPORT_SAMU |*/
0;
if (adev->asic_type == CHIP_KABINI) {
if (adev->rev_id == 0)
......
......@@ -885,7 +885,7 @@ static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
{
u32 orig, data;
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
} else {
......@@ -906,7 +906,7 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
{
u32 orig, data;
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
data |= 0x100;
if (orig != data)
......
......@@ -445,13 +445,13 @@ static int cz_dpm_init(struct amdgpu_device *adev)
pi->gfx_pg_threshold = 500;
pi->caps_fps = true;
/* uvd */
pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;