Commit c3a416a6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-next' of git://

Pull i2c updates from Wolfram Sang:
 "Most notable:

   - introducing the i2c_quirk infrastructure.  Now, flaws of I2C
     controllers can be described and the core will check if the flaws
     collide with the messages to be sent

   - wait_for_completion return type cleanup series

   - new drivers for Digicolor, Netlogic XLP, Ingenic JZ4780

   - updates to the I2C slave framework which include API changes.  Its
     only user was updated, too.  Documentation was finally added

   - changed dynamic bus numbering for the DT case.  This could change
     bus numbers for users.  However, it fixes a collision where dynamic
     and static busses request the same id.

   - driver bugfixes, cleanups"

* 'i2c/for-next' of git:// (52 commits)
  i2c: xlp9xx: Driver for Netlogic XLP9XX/5XX I2C controller
  of: Add vendor prefix 'netlogic'
  i2c: davinci: use ICPFUNC to toggle I2C as gpio for bus recovery
  i2c: davinci: use bus recovery infrastructure
  i2c: change input parameter to i2c_adapter for prepare/unprepare_recovery
  i2c: i2c-mux-gpio: remove error messages for probe deferrals
  i2c: jz4780: Add i2c bus controller driver for Ingenic JZ4780
  i2c: dln2: set the device tree node of the adapter
  i2c: davinci: fixup wait_for_completion_timeout handling
  i2c: mpc: Fix ISR return value
  i2c: slave-eeprom: add more info when to increase the pointer
  i2c: slave: add documentation for i2c-slave-eeprom
  Documentation: i2c: describe the new slave mode
  i2c: slave: rework the slave API
  i2c: add support for the Digicolor I2C controller
  i2c: busses with dynamic ids should start after fixed ids for DT
  of: base: add function to get highest id of an alias stem
  i2c: designware: Suppress error message if platform_get_irq() < 0
  i2c: mpc: assign the correct prescaler from SVR
  i2c: img-scb: fixup of wait_for_completion_timeout return handling
parents 8c194f3b 2bbd681b
......@@ -10,6 +10,9 @@ Required properties:
Recommended properties :
- interrupts : standard interrupt property.
- clock-frequency : desired I2C bus clock frequency in Hz.
- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
registers. PFUNC registers allow to switch I2C pins to function as
GPIOs, so they can by toggled manually.
Example (enbw_cmc board):
i2c@1c22000 {
Conexant Digicolor I2C controller
Required properties:
- compatible: must be "cnxt,cx92755-i2c"
- reg: physical address and length of the device registers
- interrupts: a single interrupt specifier
- clocks: clock for the device
- #address-cells: should be <1>
- #size-cells: should be <0>
Optional properties:
- clock-frequency: the desired I2C bus clock frequency in Hz; in
absence of this property the default value is used (100 kHz).
i2c: i2c@f0000120 {
compatible = "cnxt,cx92755-i2c";
reg = <0xf0000120 0x10>;
interrupts = <28>;
clocks = <&main_clk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
* Ingenic JZ4780 I2C Bus controller
Required properties:
- compatible: should be "ingenic,jz4780-i2c"
- reg: Should contain the address & size of the I2C controller registers.
- interrupts: Should specify the interrupt provided by parent.
- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
- clock-frequency: desired I2C bus clock frequency in Hz.
Recommended properties:
- pinctrl-names: should be "default";
- pinctrl-0: phandle to pinctrl function
Optional properties:
- interrupt-parent: Should be the phandle of the interrupt controller that
delivers interrupts to the I2C block.
/ {
i2c4: i2c4@0x10054000 {
compatible = "ingenic,jz4780-i2c";
reg = <0x10054000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <56>;
clocks = <&cgu JZ4780_CLK_SMB4>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_i2c4_data>;
Device tree configuration for the I2C controller on the XLP9xx/5xx SoC
Required properties:
- compatible : should be "netlogic,xlp980-i2c"
- reg : bus address start and address range size of device
- interrupts : interrupt number
Optional properties:
- clock-frequency : frequency of bus clock in Hz
Defaults to 100 KHz when the property is not specified
i2c0: i2c@113100 {
compatible = "netlogic,xlp980-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x113100 0x100>;
clock-frequency = <400000>;
interrupts = <30>;
interrupt-parent = <&pic>;
......@@ -125,6 +125,7 @@ mxicy Macronix International Co., Ltd.
national National Semiconductor
neonode Neonode Inc.
netgear NETGEAR
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
newhaven Newhaven Display International
nintendo Nintendo
nokia Nokia
Linux I2C slave eeprom backend
by Wolfram Sang <> in 2014-15
This is a proof-of-concept backend which acts like an EEPROM on the connected
I2C bus. The memory contents can be modified from userspace via this file
located in sysfs:
As of 2015, Linux doesn't support poll on binary sysfs files, so there is no
notfication when another master changed the content.
Linux I2C slave interface description
by Wolfram Sang <> in 2014-15
Linux can also be an I2C slave in case I2C controllers have slave support.
Besides this HW requirement, one also needs a software backend providing the
actual functionality. An example for this is the slave-eeprom driver, which
acts as a dual memory driver. While another I2C master on the bus can access it
like a regular EEPROM, the Linux I2C slave can access the content via sysfs and
retrieve/provide information as needed. The software backend driver and the I2C
bus driver communicate via events. Here is a small graph visualizing the data
flow and the means by which data is transported. The dotted line marks only one
example. The backend could also use e.g. a character device, be in-kernel
only, or something completely different:
e.g. sysfs I2C slave events I/O registers
+-----------+ v +---------+ v +--------+ v +------------+
| Userspace +........+ Backend +-----------+ Driver +-----+ Controller |
+-----------+ +---------+ +--------+ +------------+
| |
----------------------------------------------------------------+-- I2C
--------------------------------------------------------------+---- Bus
Note: Technically, there is also the I2C core between the backend and the
driver. However, at this time of writing, the layer is transparent.
User manual
I2C slave backends behave like standard I2C clients. So, you can instantiate
them like described in the document 'instantiating-devices'. A quick example
for instantiating the slave-eeprom driver from userspace:
# echo 0-0064 > /sys/bus/i2c/drivers/i2c-slave-eeprom/bind
Each backend should come with separate documentation to describe its specific
behaviour and setup.
Developer manual
I2C slave events
The bus driver sends an event to the backend using the following function:
ret = i2c_slave_event(client, event, &val)
'client' describes the i2c slave device. 'event' is one of the special event
types described hereafter. 'val' holds an u8 value for the data byte to be
read/written and is thus bidirectional. The pointer to val must always be
provided even if val is not used for an event, i.e. don't use NULL here. 'ret'
is the return value from the backend. Mandatory events must be provided by the
bus drivers and must be checked for by backend drivers.
Event types:
'val': unused
'ret': always 0
Another I2C master wants to write data to us. This event should be sent once
our own address and the write bit was detected. The data did not arrive yet, so
there is nothing to process or return. Wakeup or initialization probably needs
to be done, though.
'val': backend returns first byte to be sent
'ret': always 0
Another I2C master wants to read data from us. This event should be sent once
our own address and the read bit was detected. After returning, the bus driver
should transmit the first byte.
'val': bus driver delivers received byte
'ret': 0 if the byte should be acked, some errno if the byte should be nacked
Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte
should be nacked.
'val': backend returns next byte to be sent
'ret': always 0
The bus driver requests the next byte to be sent to another I2C master in
'val'. Important: This does not mean that the previous byte has been acked, it
only means that the previous byte is shifted out to the bus! To ensure seamless
transmission, most hardware requests the next byte when the previous one is
still shifted out. If the master sends NACK and stops reading after the byte
currently shifted out, this byte requested here is never used. It very likely
needs to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on
your backend, though.
* I2C_SLAVE_STOP (mandatory)
'val': unused
'ret': always 0
A stop condition was received. This can happen anytime and the backend should
reset its state machine for I2C transfers to be able to receive new requests.
Software backends
If you want to write a software backend:
* use a standard i2c_driver and its matching mechanisms
* write the slave_callback which handles the above slave events
(best using a state machine)
* register this callback via i2c_slave_register()
Check the i2c-slave-eeprom driver as an example.
Bus driver support
If you want to add slave support to the bus driver:
* implement calls to register/unregister the slave and add those to the
struct i2c_algorithm. When registering, you probably need to set the i2c
slave address and enable slave specific interrupts. If you use runtime pm, you
should use pm_runtime_forbid() because your device usually needs to be powered
on always to be able to detect its slave address. When unregistering, do the
inverse of the above.
* Catch the slave interrupts and send appropriate i2c_slave_events to the backend.
Check the i2c-rcar driver as an example.
It is good behaviour to always ACK the address phase, so the master knows if a
device is basically present or if it mysteriously disappeared. Using NACK to
state being busy is troublesome. SMBus demands to always ACK the address phase,
while the I2C specification is more loose on that. Most I2C controllers also
automatically ACK when detecting their slave addresses, so there is no option
to NACK them. For those reasons, this API does not support NACK in the address
Currently, there is no slave event to report if the master did ACK or NACK a
byte when it reads from us. We could make this an optional event if the need
arises. However, cases should be extremely rare because the master is expected
to send STOP after that and we have an event for that. Also, keep in mind not
all I2C controllers have the possibility to report that event.
About buffers
During development of this API, the question of using buffers instead of just
bytes came up. Such an extension might be possible, usefulness is unclear at
this time of writing. Some points to keep in mind when using buffers:
* Buffers should be opt-in and slave drivers will always have to support
byte-based transactions as the ultimate fallback because this is how the
majority of HW works.
* For backends simulating hardware registers, buffers are not helpful because
on writes an action should be immediately triggered. For reads, the data in
the buffer might get stale.
* A master can send STOP at any time. For partially transferred buffers, this
means additional code to handle this exception. Such code tends to be
......@@ -41,7 +41,3 @@ integrated than Algorithm and Adapter.
For a given configuration, you will need a driver for your I2C bus, and
drivers for your I2C devices (usually one driver for each device).
At this time, Linux only operates I2C (or SMBus) in master mode; you can't
use these APIs to make a Linux system behave as a slave/device, either to
speak a custom protocol or to emulate some other device.
......@@ -485,6 +485,15 @@ config I2C_DESIGNWARE_BAYTRAIL
the platform firmware controlling it. You should say Y if running on
a BayTrail system using the AXP288.
tristate "Conexant Digicolor I2C driver"
Support for Conexant Digicolor SoCs (CX92755) I2C controller driver.
This driver can also be built as a module. If so, the module
will be called i2c-digicolor.
config I2C_EFM32
tristate "EFM32 I2C controller"
depends on ARCH_EFM32 || COMPILE_TEST
......@@ -574,6 +583,15 @@ config I2C_IOP3XX
This driver can also be built as a module. If so, the module
will be called i2c-iop3xx.
config I2C_JZ4780
tristate "JZ4780 I2C controller interface support"
depends on MACH_JZ4780 || COMPILE_TEST
If you say yes to this option, support will be included for the
Ingenic JZ4780 I2C controller.
If you don't know what to do here, say N.
config I2C_KEMPLD
tristate "Kontron COM I2C Controller"
depends on MFD_KEMPLD
......@@ -898,6 +916,16 @@ config I2C_XLR
This driver can also be built as a module. If so, the module
will be called i2c-xlr.
config I2C_XLP9XX
tristate "XLP9XX I2C support"
depends on CPU_XLP || COMPILE_TEST
This driver enables support for the on-chip I2C interface of
the Broadcom XLP9xx/XLP5xx MIPS processors.
This driver can also be built as a module. If so, the module will
be called i2c-xlp9xx.
config I2C_RCAR
tristate "Renesas R-Car I2C Controller"
......@@ -45,6 +45,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
i2c-designware-pci-objs := i2c-designware-pcidrv.o
obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
......@@ -55,6 +56,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
obj-$(CONFIG_I2C_MESON) += i2c-meson.o
obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
......@@ -87,6 +89,7 @@ obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
# External I2C/SMBus adapter drivers
......@@ -381,6 +381,7 @@ static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
static int at91_do_twi_transfer(struct at91_twi_dev *dev)
int ret;
unsigned long time_left;
bool has_unre_flag = dev->pdata->has_unre_flag;
dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
......@@ -436,9 +437,9 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
ret = wait_for_completion_timeout(&dev->cmd_complete,
if (ret == 0) {
time_left = wait_for_completion_timeout(&dev->cmd_complete,
if (time_left == 0) {
dev_err(dev->dev, "controller timed out\n");
......@@ -487,30 +488,10 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
if (ret < 0)
goto out;
* The hardware can handle at most two messages concatenated by a
* repeated start via it's internal address feature.
if (num > 2) {
"cannot handle more than two concatenated messages.\n");
ret = 0;
goto out;
} else if (num == 2) {
if (num == 2) {
int internal_address = 0;
int i;
if (msg->flags & I2C_M_RD) {
dev_err(dev->dev, "first transfer must be write.\n");
ret = -EINVAL;
goto out;
if (msg->len > 3) {
dev_err(dev->dev, "first message size must be <= 3.\n");
ret = -EINVAL;
goto out;
/* 1st msg is put into the internal address, start with 2nd */
m_start = &msg[1];
for (i = 0; i < msg->len; ++i) {
......@@ -540,6 +521,15 @@ out:
return ret;
* The hardware can handle at most two messages concatenated by a
* repeated start via it's internal address feature.
static struct i2c_adapter_quirks at91_twi_quirks = {
.max_comb_1st_msg_len = 3,
static u32 at91_twi_func(struct i2c_adapter *adapter)
......@@ -777,6 +767,7 @@ static int at91_twi_probe(struct platform_device *pdev)
dev->adapter.owner = THIS_MODULE;
dev->adapter.class = I2C_CLASS_DEPRECATED;
dev->adapter.algo = &at91_twi_algorithm;
dev->adapter.quirks = &at91_twi_quirks;
dev-> = dev->dev;
dev-> = pdev->id;
dev->adapter.timeout = AT91_I2C_TIMEOUT;
......@@ -334,12 +334,7 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
u32 rx_xfer, tx_xfer;
u32 addr_1, addr_2;
int ret;
if (msg->len > 255) {
dev_warn(idev->dev, "unsupported length %u\n", msg->len);
return -EINVAL;
unsigned long time_left;
idev->msg = msg;
idev->msg_xfrd = 0;
......@@ -388,15 +383,15 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
i2c_int_enable(idev, int_mask);
ret = wait_for_completion_timeout(&idev->msg_complete,
time_left = wait_for_completion_timeout(&idev->msg_complete,
i2c_int_disable(idev, int_mask);
if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
dev_warn(idev->dev, "busy after xfer\n");
if (ret == 0)
if (time_left == 0)
idev->msg_err = -ETIMEDOUT;
if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
......@@ -408,17 +403,17 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
int ret;
unsigned long time_left;
/* Issue stop */
writel(0xb, idev->base + MST_COMMAND);
i2c_int_enable(idev, int_mask);
ret = wait_for_completion_timeout(&idev->msg_complete,
time_left = wait_for_completion_timeout(&idev->msg_complete,
i2c_int_disable(idev, int_mask);
if (ret == 0)
if (time_left == 0)
return -ETIMEDOUT;
if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
......@@ -454,6 +449,11 @@ static const struct i2c_algorithm axxia_i2c_algo = {
.functionality = axxia_i2c_func,
static struct i2c_adapter_quirks axxia_i2c_quirks = {
.max_read_len = 255,
.max_write_len = 255,
static int axxia_i2c_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
......@@ -511,6 +511,7 @@ static int axxia_i2c_probe(struct platform_device *pdev)
strlcpy(idev->, pdev->name, sizeof(idev->;
idev->adapter.owner = THIS_MODULE;
idev->adapter.algo = &axxia_i2c_algo;
idev->adapter.quirks = &axxia_i2c_quirks;
idev-> = &pdev->dev;
idev-> = pdev->dev.of_node;
......@@ -160,14 +160,6 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
u32 val;
unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC);
/* need to reserve one byte in the FIFO for the slave address */
if (msg->len > M_TX_RX_FIFO_SIZE - 1) {
"only support data length up to %u bytes\n",
/* check if bus is busy */
if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
......@@ -287,6 +279,12 @@ static const struct i2c_algorithm bcm_iproc_algo = {
.functionality = bcm_iproc_i2c_functionality,
static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
/* need to reserve one byte in the FIFO for the slave address */
.max_read_len = M_TX_RX_FIFO_SIZE - 1,
.max_write_len = M_TX_RX_FIFO_SIZE - 1,
static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
unsigned int bus_speed;
......@@ -413,6 +411,7 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
i2c_set_adapdata(adap, iproc_i2c);
strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
adap->algo = &bcm_iproc_algo;
adap->quirks = &bcm_iproc_i2c_quirks;
adap->dev.parent = &pdev->dev;
adap->dev.of_node = pdev->dev.of_node;
......@@ -147,7 +147,7 @@ static int bcm2835_i2c_xfer_msg(struct bcm2835_i2c_dev *i2c_dev,
struct i2c_msg *msg)
u32 c;
int time_left;
unsigned long time_left;
i2c_dev->msg_buf = msg->buf;
i2c_dev->msg_buf_remaining = msg->len;
......@@ -475,7 +475,7 @@ static void cdns_i2c_master_reset(struct i2c_adapter *adap)
static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
struct i2c_adapter *adap)
int ret;
unsigned long time_left;
u32 reg;
id->p_msg = msg;
......@@ -501,8 +501,8 @@ static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
/* Wait for the signal of completion */
ret = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
if (!ret) {
time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
if (time_left == 0) {
"timeout waiting on completion\n");
......@@ -308,22 +308,12 @@ static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
struct i2c_msg *pmsg;
int ret, i;
int ret;
int tptr;
int rptr;
cbd_t __iomem *tbdf;
cbd_t __iomem *rbdf;
if (num > CPM_MAXBD)
return -EINVAL;
/* Check if we have any oversized READ requests */
for (i = 0; i < num; i++) {
pmsg = &msgs[i];
if (pmsg->len >= CPM_MAX_READ)
return -EINVAL;
/* Reset to use first buffer */
out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));