Commit becd2142 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50: use alternate source of SOR_MODE_CTRL for DP hack



Fixes module unload+reload on Dell M4500, where the "normal" registers
get reset to 0.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 26099a74
...@@ -274,7 +274,6 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = { ...@@ -274,7 +274,6 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
int int
nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_encoder *nv_encoder = NULL; struct nouveau_encoder *nv_encoder = NULL;
struct drm_encoder *encoder; struct drm_encoder *encoder;
bool dum; bool dum;
...@@ -324,11 +323,7 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) ...@@ -324,11 +323,7 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
int or = nv_encoder->or, link = !(entry->dpconf.sor.link & 1); int or = nv_encoder->or, link = !(entry->dpconf.sor.link & 1);
uint32_t tmp; uint32_t tmp;
if (dev_priv->chipset < 0x90 || tmp = nv_rd32(dev, 0x61c700 + (or * 0x800));
dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
else
tmp = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
switch ((tmp & 0x00000f00) >> 8) { switch ((tmp & 0x00000f00) >> 8) {
case 8: case 8:
......
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