Commit bec50527 authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle
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[MIPS] Tidy up cache attributes


Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 962f480e
...@@ -47,15 +47,9 @@ ...@@ -47,15 +47,9 @@
#define _PAGE_SILENT_READ (1<<1) /* synonym */ #define _PAGE_SILENT_READ (1<<1) /* synonym */
#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ #define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
#define _PAGE_SILENT_WRITE (1<<2) #define _PAGE_SILENT_WRITE (1<<2)
#define _CACHE_SHIFT 3
#define _CACHE_MASK (7<<3) #define _CACHE_MASK (7<<3)
/* MIPS32 defines only values 2 and 3. The rest are implementation
* dependent.
*/
#define _CACHE_UNCACHED (2<<3)
#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
#else #else
#define _PAGE_PRESENT (1<<0) /* implemented in software */ #define _PAGE_PRESENT (1<<0) /* implemented in software */
...@@ -74,55 +68,66 @@ ...@@ -74,55 +68,66 @@
#define _PAGE_SILENT_WRITE (1<<10) #define _PAGE_SILENT_WRITE (1<<10)
#define _CACHE_UNCACHED (1<<11) #define _CACHE_UNCACHED (1<<11)
#define _CACHE_MASK (1<<11) #define _CACHE_MASK (1<<11)
#define _CACHE_CACHABLE_NONCOHERENT 0
#else #else
#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
#define _PAGE_GLOBAL (1<<6) #define _PAGE_GLOBAL (1<<6)
#define _PAGE_VALID (1<<7) #define _PAGE_VALID (1<<7)
#define _PAGE_SILENT_READ (1<<7) /* synonym */ #define _PAGE_SILENT_READ (1<<7) /* synonym */
#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
#define _PAGE_SILENT_WRITE (1<<8) #define _PAGE_SILENT_WRITE (1<<8)
#define _CACHE_SHIFT 9
#define _CACHE_MASK (7<<9) #define _CACHE_MASK (7<<9)
#ifdef CONFIG_CPU_SB1 #endif
#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
/*
* Cache attributes
*/
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
#define _CACHE_CACHABLE_NONCOHERENT 0
#elif defined(CONFIG_CPU_SB1)
/* No penalty for being coherent on the SB1, so just /* No penalty for being coherent on the SB1, so just
use it for "noncoherent" spaces, too. Shouldn't hurt. */ use it for "noncoherent" spaces, too. Shouldn't hurt. */
#define _CACHE_UNCACHED (2<<9) #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW (5<<9) #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (5<<9) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
#define _CACHE_UNCACHED_ACCELERATED (7<<9) #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#elif defined(CONFIG_CPU_RM9000) #elif defined(CONFIG_CPU_RM9000)
#define _CACHE_WT (0 << 9) #define _CACHE_WT (0<<_CACHE_SHIFT)
#define _CACHE_WTWA (1 << 9) #define _CACHE_WTWA (1<<_CACHE_SHIFT)
#define _CACHE_UC_B (2 << 9) #define _CACHE_UC_B (2<<_CACHE_SHIFT)
#define _CACHE_WB (3 << 9) #define _CACHE_WB (3<<_CACHE_SHIFT)
#define _CACHE_CWBEA (4 << 9) #define _CACHE_CWBEA (4<<_CACHE_SHIFT)
#define _CACHE_CWB (5 << 9) #define _CACHE_CWB (5<<_CACHE_SHIFT)
#define _CACHE_UCNB (6 << 9) #define _CACHE_UCNB (6<<_CACHE_SHIFT)
#define _CACHE_FPC (7 << 9) #define _CACHE_FPC (7<<_CACHE_SHIFT)
#define _CACHE_UNCACHED _CACHE_UC_B #define _CACHE_UNCACHED _CACHE_UC_B
#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB #define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
#else #else
#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ #define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
#endif #endif
#endif
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
...@@ -135,14 +140,12 @@ ...@@ -135,14 +140,12 @@
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
#elif defined(CONFIG_CPU_RM9000) #elif defined(CONFIG_CPU_RM9000)
#define PAGE_CACHABLE_DEFAULT _CACHE_CWB #define PAGE_CACHABLE_DEFAULT _CACHE_CWB
#elif defined(CONFIG_SOC_AU1X00)
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
#else #else
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
#endif #endif
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
#else
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
#endif
#endif /* _ASM_PGTABLE_BITS_H */ #endif /* _ASM_PGTABLE_BITS_H */
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