Commit bc23100a authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote-tracking branch 'kumar/next' into next

From Kumar Gala:
<<
Add support for T4 and B4 SoC families from Freescale, e6500 altivec
support, some various board fixes and other minor cleanups.
>>
parents 28bf41a1 9e2ecdbb
===================================================================
Power Architecture CPU Binding
Copyright 2013 Freescale Semiconductor Inc.
Power Architecture CPUs in Freescale SOCs are represented in device trees as
per the definition in ePAPR.
In addition to the ePAPR definitions, the properties defined below may be
present on CPU nodes.
PROPERTIES
- fsl,eref-*
Usage: optional
Value type: <empty>
Definition: The EREF (EREF: A Programmer.s Reference Manual for
Freescale Power Architecture) defines the architecture for Freescale
Power CPUs. The EREF defines some architecture categories not defined
by the Power ISA. For these EREF-specific categories, the existence of
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
name with all uppercase letters converted to lowercase, indicates that
the category is supported by the implementation.
......@@ -681,7 +681,6 @@ config SBUS
config FSL_SOC
bool
select HAVE_CAN_FLEXCAN if NET && CAN
select PPC_CLOCK
config FSL_PCI
bool
......@@ -769,11 +768,6 @@ config PCI_8260
select PPC_INDIRECT_PCI
default y
config 8260_PCI9
bool "Enable workaround for MPC826x erratum PCI 9"
depends on PCI_8260 && !8272
default y
source "drivers/pci/pcie/Kconfig"
source "drivers/pci/Kconfig"
......
/*
* B4420DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/include/ "fsl/b4420si-pre.dtsi"
/include/ "b4qds.dts"
/ {
model = "fsl,B4420QDS";
compatible = "fsl,B4420QDS";
ifc: localbus@ffe124000 {
board-control@3,0 {
compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
};
};
};
/include/ "fsl/b4420si-post.dtsi"
/*
* B4860DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/b4860si-pre.dtsi"
/include/ "b4qds.dts"
/ {
model = "fsl,B4860QDS";
compatible = "fsl,B4860QDS";
ifc: localbus@ffe124000 {
board-control@3,0 {
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
};
};
rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>;
port1 {
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
};
port2 {
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
};
};
};
/include/ "fsl/b4860si-post.dtsi"
/*
* B4420DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/ {
model = "fsl,B4QDS";
compatible = "fsl,B4QDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xff800000 0x00010000
3 0 0xf 0xffdf0000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 10MB for Linux Kernel Image */
reg = <0x00200000 0x00A00000>;
label = "NAND Linux Kernel Image";
};
partition@c00000 {
/* 500MB for Root file System Image */
reg = <0x00c00000 0x1F400000>;
label = "NAND RFS Image";
};
};
board-control@3,0 {
compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
reg = <3 0 0x300>;
};
};
memory {
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01052000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf040";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
};
};
sdhc@114000 {
/*Disabled as there is no sdhc connector on B4420QDS board*/
status = "disabled";
};
i2c@118000 {
eeprom@50 {
compatible = "at24,24c64";
reg = <0x50>;
};
eeprom@51 {
compatible = "at24,24c256";
reg = <0x51>;
};
eeprom@53 {
compatible = "at24,24c256";
reg = <0x53>;
};
eeprom@57 {
compatible = "at24,24c256";
reg = <0x57>;
};
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
usb@210000 {
dr_mode = "host";
phy_type = "ulpi";
};
};
pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
};
/include/ "fsl/b4si-post.dtsi"
/*
* B4420 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/include/ "b4si-post.dtsi"
/* controller at 0x200000 */
&pci0 {
compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
};
&dcsr {
dcsr-epu@0 {
compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
};
dcsr-npc {
compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
};
dcsr-dpaa@9000 {
compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
};
dcsr-ocn@11000 {
compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
};
dcsr-nal@18000 {
compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
};
dcsr-rcpm@22000 {
compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
};
dcsr-snpc@30000 {
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-snpc@31000 {
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-cpu-sb-proxy@108000 {
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x108000 0x1000 0x109000 0x1000>;
};
};
&soc {
cpc: l3-cache-controller@10000 {
compatible = "fsl,b4420-l3-cache-controller", "cache";
};
corenet-cf@18000 {
compatible = "fsl,b4420-corenet-cf";
};
guts: global-utilities@e0000 {
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
};
clockgen: global-utilities@e1000 {
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
};
rcpm: global-utilities@e2000 {
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
};
L2: l2-cache-controller@c20000 {
compatible = "fsl,b4420-l2-cache-controller";
};
};
/*
* B4420 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/dts-v1/;
/ {
compatible = "fsl,B4420";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
dma0 = &dma0;
dma1 = &dma1;
sdhc = &sdhc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
next-level-cache = <&L2>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2>;
};
};
};
/*
* B4860 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "b4si-post.dtsi"
/* controller at 0x200000 */
&pci0 {
compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
};
&rio {
compatible = "fsl,srio";
interrupts = <16 2 1 11>;
#address-cells = <2>;
#size-cells = <2>;
fsl,iommu-parent = <&pamu0>;
ranges;
port1 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <1>;
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
};
port2 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <2>;
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
};
};
&dcsr {
dcsr-epu@0 {
compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
};
dcsr-npc {
compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
};
dcsr-dpaa@9000 {
compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
};
dcsr-ocn@11000 {
compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
};
dcsr-ddr@13000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr2>;
reg = <0x13000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
};
dcsr-rcpm@22000 {
compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
};
dcsr-snpc@30000 {
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-snpc@31000 {
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
};
dcsr-cpu-sb-proxy@108000 {
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x108000 0x1000 0x109000 0x1000>;
};
dcsr-cpu-sb-proxy@110000 {
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x110000 0x1000 0x111000 0x1000>;
};
dcsr-cpu-sb-proxy@118000 {
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x118000 0x1000 0x119000 0x1000>;
};
};