Commit bbecce8d authored by Linus Torvalds's avatar Linus Torvalds

Merge git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:

 - MIPS didn't define the new ioremap_uc.  Defined it as an alias for
   ioremap_uncached.

 - Replace workaround for MIPS16 build issue with a correct one.

* git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Define ioremap_uc
  MIPS: UAPI: Ignore __arch_swab{16,32,64} when using MIPS16
  Revert "MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16."
parents 1d8a12d1 da11f98f
...@@ -256,6 +256,7 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si ...@@ -256,6 +256,7 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si
*/ */
#define ioremap_nocache(offset, size) \ #define ioremap_nocache(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED) __ioremap_mode((offset), (size), _CACHE_UNCACHED)
#define ioremap_uc ioremap_nocache
/* /*
* ioremap_cachable - map bus memory into CPU space * ioremap_cachable - map bus memory into CPU space
......
...@@ -13,16 +13,15 @@ ...@@ -13,16 +13,15 @@
#define __SWAB_64_THRU_32__ #define __SWAB_64_THRU_32__
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ #if !defined(__mips16) && \
defined(_MIPS_ARCH_LOONGSON3A) ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \
defined(_MIPS_ARCH_LOONGSON3A))
static inline __attribute__((nomips16)) __attribute_const__ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
__u16 __arch_swab16(__u16 x)
{ {
__asm__( __asm__(
" .set push \n" " .set push \n"
" .set arch=mips32r2 \n" " .set arch=mips32r2 \n"
" .set nomips16 \n"
" wsbh %0, %1 \n" " wsbh %0, %1 \n"
" .set pop \n" " .set pop \n"
: "=r" (x) : "=r" (x)
...@@ -32,13 +31,11 @@ static inline __attribute__((nomips16)) __attribute_const__ ...@@ -32,13 +31,11 @@ static inline __attribute__((nomips16)) __attribute_const__
} }
#define __arch_swab16 __arch_swab16 #define __arch_swab16 __arch_swab16
static inline __attribute__((nomips16)) __attribute_const__ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
__u32 __arch_swab32(__u32 x)
{ {
__asm__( __asm__(
" .set push \n" " .set push \n"
" .set arch=mips32r2 \n" " .set arch=mips32r2 \n"
" .set nomips16 \n"
" wsbh %0, %1 \n" " wsbh %0, %1 \n"
" rotr %0, %0, 16 \n" " rotr %0, %0, 16 \n"
" .set pop \n" " .set pop \n"
...@@ -54,13 +51,11 @@ static inline __attribute__((nomips16)) __attribute_const__ ...@@ -54,13 +51,11 @@ static inline __attribute__((nomips16)) __attribute_const__
* 64-bit kernel on r2 CPUs. * 64-bit kernel on r2 CPUs.
*/ */
#ifdef __mips64 #ifdef __mips64
static inline __attribute__((nomips16)) __attribute_const__ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
__u64 __arch_swab64(__u64 x)
{ {
__asm__( __asm__(
" .set push \n" " .set push \n"
" .set arch=mips64r2 \n" " .set arch=mips64r2 \n"
" .set nomips16 \n"
" dsbh %0, %1 \n" " dsbh %0, %1 \n"
" dshd %0, %0 \n" " dshd %0, %0 \n"
" .set pop \n" " .set pop \n"
...@@ -71,5 +66,5 @@ static inline __attribute__((nomips16)) __attribute_const__ ...@@ -71,5 +66,5 @@ static inline __attribute__((nomips16)) __attribute_const__
} }
#define __arch_swab64 __arch_swab64 #define __arch_swab64 __arch_swab64
#endif /* __mips64 */ #endif /* __mips64 */
#endif /* MIPS R2 or newer or Loongson 3A */ #endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */
#endif /* _ASM_SWAB_H */ #endif /* _ASM_SWAB_H */
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