Commit b17879f7 authored by Josh Boyer's avatar Josh Boyer Committed by Paul Mackerras
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[POWERPC] 4xx: Clear new TLB cache attribute bits in Data Storage vector



A recent commit added support for the new 440x6 and 464 cores that have the
added WL1, IL1I, IL1D, IL2I, and ILD2 bits for the caching attributes in the
TLBs.  The new bits were cleared in the finish_tlb_load function, however a
similar bit of code was missed in the DataStorage interrupt vector.
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 952f4a0a
......@@ -368,7 +368,12 @@ interrupt_base:
rlwimi r11,r13,0,26,31 /* Insert static perms */
rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
/*
* Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
* on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
* include/asm-powerpc/pgtable-ppc32.h for details).
*/
rlwinm r11,r11,0,20,10
/* find the TLB index that caused the fault. It has to be here. */
tlbsx r10, 0, r10
......
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