Commit a9da4f7e authored by Russell King's avatar Russell King Committed by Russell King

Merge branches 'pxa-ian' and 'pxa-xm270' into pxa

Conflicts:

	MAINTAINERS
......@@ -475,28 +475,34 @@ M: kernel@wantstofly.org
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/COMPULAB CM-X270/EM-X270 MACHINE SUPPORT
P: Mike Rapoport
M: mike@compulab.co.il
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/CORGI MACHINE SUPPORT
P: Richard Purdie
M: rpurdie@rpsys.net
S: Maintained
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
P: Daniel Ribeiro
M: drwyrm@gmail.com
P: Stefan Schmidt
M: stefan@openezx.org
P: Harald Welte
M: laforge@openezx.org
L: openezx-devel@lists.openezx.org (subscribers-only)
W: http://www.openezx.org/
S: Maintained
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
P: Lennert Buytenhek
M: kernel@wantstofly.org
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
P: Daniel Ribeiro
M: drwyrm@gmail.com
P: Stefan Schmidt
M: stefan@openezx.org
P: Harald Welte
M: laforge@openezx.org
L: openezx-devel@lists.openezx.org (subscribers-only)
W: http://www.openezx.org/
S: Maintained
ARM/GUMSTIX MACHINE SUPPORT
P: Steve Sakoman
M: sakoman@gmail.com
......
......@@ -627,7 +627,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
if (!sachip)
return -ENOMEM;
sachip->clk = clk_get(me, "GPIO27_CLK");
sachip->clk = clk_get(me, "SA1111_CLK");
if (!sachip->clk) {
ret = PTR_ERR(sachip->clk);
goto err_free;
......
......@@ -101,21 +101,6 @@ unsigned long clk_get_rate(struct clk *clk)
EXPORT_SYMBOL(clk_get_rate);
static void clk_gpio27_enable(struct clk *clk)
{
pxa_gpio_mode(GPIO11_3_6MHz_MD);
}
static void clk_gpio27_disable(struct clk *clk)
{
}
static const struct clkops clk_gpio27_ops = {
.enable = clk_gpio27_enable,
.disable = clk_gpio27_disable,
};
void clk_cken_enable(struct clk *clk)
{
CKEN |= 1 << clk->cken;
......@@ -131,14 +116,6 @@ const struct clkops clk_cken_ops = {
.disable = clk_cken_disable,
};
static struct clk common_clks[] = {
{
.name = "GPIO27_CLK",
.ops = &clk_gpio27_ops,
.rate = 3686400,
},
};
void clks_register(struct clk *clks, size_t num)
{
int i;
......@@ -148,10 +125,3 @@ void clks_register(struct clk *clks, size_t num)
list_add(&clks[i].node, &clocks);
mutex_unlock(&clocks_mutex);
}
static int __init clk_init(void)
{
clks_register(common_clks, ARRAY_SIZE(common_clks));
return 0;
}
arch_initcall(clk_init);
......@@ -47,6 +47,15 @@ struct clk {
.other = _other, \
}
#define INIT_CLK(_name, _ops, _rate, _delay, _dev) \
{ \
.name = _name, \
.dev = _dev, \
.ops = _ops, \
.rate = _rate, \
.delay = _delay, \
}
extern const struct clkops clk_cken_ops;
void clk_cken_enable(struct clk *clk);
......
......@@ -5,7 +5,7 @@
*
* Bits taken from various places.
*
* Copyright (C) 2007 Compulab, Ltd.
* Copyright (C) 2007, 2008 Compulab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
......@@ -19,16 +19,16 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach/pci.h>
#include <asm/arch/cm-x270.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/mach-types.h>
#include <asm/hardware/it8152.h>
unsigned long it8152_base_address = CMX270_IT8152_VIRT;
unsigned long it8152_base_address;
static int cmx270_it8152_irq_gpio;
/*
* Only first 64MB of memory can be accessed via PCI.
......@@ -42,7 +42,7 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
unsigned int sz = SZ_64M >> PAGE_SHIFT;
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-x270\n");
pr_info("Adjusting zones for CM-X270\n");
/*
* Only adjust if > 64M on current system
......@@ -60,19 +60,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
/* clear our parent irq */
GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio);
it8152_irq_demux(irq, desc);
}
void __cmx270_pci_init_irq(void)
void __cmx270_pci_init_irq(int irq_gpio)
{
it8152_init_irq();
pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
cmx270_it8152_irq_demux);
cmx270_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
}
#ifdef CONFIG_PM
......@@ -115,8 +116,8 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/*
Here comes the ugly part. The routing is baseboard specific,
but defining a platform for each possible base of CM-x270 is
unrealistic. Here we keep mapping for ATXBase and SB-x270.
but defining a platform for each possible base of CM-X270 is
unrealistic. Here we keep mapping for ATXBase and SB-X270.
*/
/* ATXBASE PCI slot */
if (slot == 7)
......
extern void __cmx270_pci_init_irq(void);
extern void __cmx270_pci_init_irq(int irq_gpio);
extern void __cmx270_pci_suspend(void);
extern void __cmx270_pci_resume(void);
#ifdef CONFIG_PCI
#define cmx270_pci_init_irq __cmx270_pci_init_irq
#define cmx270_pci_suspend __cmx270_pci_suspend
#define cmx270_pci_resume __cmx270_pci_resume
#define cmx270_pci_init_irq(x) __cmx270_pci_init_irq(x)
#define cmx270_pci_suspend(x) __cmx270_pci_suspend(x)
#define cmx270_pci_resume(x) __cmx270_pci_resume(x)
#else
#define cmx270_pci_init_irq() do {} while (0)
#define cmx270_pci_suspend() do {} while (0)
#define cmx270_pci_resume() do {} while (0)
#define cmx270_pci_init_irq(x) do {} while (0)
#define cmx270_pci_suspend(x) do {} while (0)
#define cmx270_pci_resume(x) do {} while (0)
#endif
This diff is collapsed.
This diff is collapsed.
......@@ -109,6 +109,52 @@ static const struct clkops clk_pxa25x_lcd_ops = {
.getrate = clk_pxa25x_lcd_getrate,
};
static unsigned long gpio12_config_32k[] = {
GPIO12_32KHz,
};
static unsigned long gpio12_config_gpio[] = {
GPIO12_GPIO,
};
static void clk_gpio12_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_32k, 1);
}
static void clk_gpio12_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio12_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio12_ops = {
.enable = clk_gpio12_enable,
.disable = clk_gpio12_disable,
};
static unsigned long gpio11_config_3m6[] = {
GPIO11_3_6MHz,
};
static unsigned long gpio11_config_gpio[] = {
GPIO11_GPIO,
};
static void clk_gpio11_enable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_3m6, 1);
}
static void clk_gpio11_disable(struct clk *clk)
{
pxa2xx_mfp_config(gpio11_config_gpio, 1);
}
static const struct clkops clk_pxa25x_gpio11_ops = {
.enable = clk_gpio11_enable,
.disable = clk_gpio11_disable,
};
/*
* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
......@@ -128,6 +174,8 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL),
INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL),
INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
......@@ -145,7 +193,10 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};
static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
static struct clk pxa2xx_clk_aliases[] = {
INIT_CKOTHER("GPIO7_CLK", &pxa25x_clks[4], NULL),
INIT_CKOTHER("SA1111_CLK", &pxa25x_clks[5], NULL),
};
#ifdef CONFIG_PM
......@@ -293,7 +344,7 @@ static int __init pxa25x_init(void)
int i, ret = 0;
/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
if (cpu_is_pxa25x())
if (cpu_is_pxa255())
clks_register(&pxa25x_hwuart_clk, 1);
if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
......@@ -317,10 +368,10 @@ static int __init pxa25x_init(void)
}
/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
if (cpu_is_pxa25x())
if (cpu_is_pxa255())
ret = platform_device_register(&pxa_device_hwuart);
clks_register(&gpio7_clk, 1);
clks_register(pxa2xx_clk_aliases, ARRAY_SIZE(pxa2xx_clk_aliases));
return ret;
}
......
......@@ -103,7 +103,7 @@ static void clk_gpio27_disable(void)
}
static struct clk clk_gpio27 = {
.name = "GPIO27_CLK",
.name = "SA1111_CLK",
.rate = 3686400,
.enable = clk_gpio27_enable,
.disable = clk_gpio27_disable,
......
......@@ -20,9 +20,11 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
......@@ -30,20 +32,6 @@
#define GPIO_NAND_CS (11)
#define GPIO_NAND_RB (89)
/* This macro needed to ensure in-order operation of GPIO and local
* bus. Without both asm command and dummy uncached read there're
* states when NAND access is broken. I've looked for such macro(s) in
* include/asm-arm but found nothing approptiate.
* dmac_clean_range is close, but is makes cache invalidation
* unnecessary here and it cannot be used in module
*/
#define DRAIN_WB() \
do { \
unsigned char dummy; \
asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0"); \
dummy=*((unsigned char*)UNCACHED_ADDR); \
} while(0)
/* MTD structure for CM-X270 board */
static struct mtd_info *cmx270_nand_mtd;
......@@ -103,14 +91,14 @@ static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
static inline void nand_cs_on(void)
{
GPCR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO_NAND_CS, 0);
}
static void nand_cs_off(void)
{
DRAIN_WB();
dsb();
GPSR(GPIO_NAND_CS) = GPIO_bit(GPIO_NAND_CS);
gpio_set_value(GPIO_NAND_CS, 1);
}
/*
......@@ -122,7 +110,7 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
struct nand_chip* this = mtd->priv;
unsigned int nandaddr = (unsigned int)this->IO_ADDR_W;
DRAIN_WB();
dsb();
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_ALE )
......@@ -139,12 +127,12 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
nand_cs_off();
}
DRAIN_WB();
dsb();
this->IO_ADDR_W = (void __iomem*)nandaddr;
if (dat != NAND_CMD_NONE)
writel((dat << 16), this->IO_ADDR_W);
DRAIN_WB();
dsb();
}
/*
......@@ -152,9 +140,9 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
*/
static int cmx270_device_ready(struct mtd_info *mtd)
{
DRAIN_WB();
dsb();
return (GPLR(GPIO_NAND_RB) & GPIO_bit(GPIO_NAND_RB));
return (gpio_get_value(GPIO_NAND_RB));
}
/*
......@@ -168,20 +156,40 @@ static int cmx270_init(void)
int mtd_parts_nb = 0;
int ret;
if (!machine_is_armcore())
return -ENODEV;
ret = gpio_request(GPIO_NAND_CS, "NAND CS");
if (ret) {
pr_warning("CM-X270: failed to request NAND CS gpio\n");
return ret;
}
gpio_direction_output(GPIO_NAND_CS, 1);
ret = gpio_request(GPIO_NAND_RB, "NAND R/B");
if (ret) {
pr_warning("CM-X270: failed to request NAND R/B gpio\n");
goto err_gpio_request;
}
gpio_direction_input(GPIO_NAND_RB);
/* Allocate memory for MTD device structure and private data */
cmx270_nand_mtd = kzalloc(sizeof(struct mtd_info) +
sizeof(struct nand_chip),
GFP_KERNEL);
if (!cmx270_nand_mtd) {
printk("Unable to allocate CM-X270 NAND MTD device structure.\n");
return -ENOMEM;
pr_debug("Unable to allocate CM-X270 NAND MTD device structure.\n");
ret = -ENOMEM;
goto err_kzalloc;
}
cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);
if (!cmx270_nand_io) {
printk("Unable to ioremap NAND device\n");
pr_debug("Unable to ioremap NAND device\n");
ret = -EINVAL;
goto err1;
goto err_ioremap;
}
/* Get pointer to private data */
......@@ -209,9 +217,9 @@ static int cmx270_init(void)
/* Scan to find existence of the device */
if (nand_scan (cmx270_nand_mtd, 1)) {
printk(KERN_NOTICE "No NAND device\n");
pr_notice("No NAND device\n");
ret = -ENXIO;
goto err2;
goto err_scan;
}
#ifdef CONFIG_MTD_CMDLINE_PARTS
......@@ -229,18 +237,22 @@ static int cmx270_init(void)
}
/* Register the partitions */
printk(KERN_NOTICE "Using %s partition definition\n", part_type);
pr_notice("Using %s partition definition\n", part_type);
ret = add_mtd_partitions(cmx270_nand_mtd, mtd_parts, mtd_parts_nb);
if (ret)
goto err2;
goto err_scan;
/* Return happy */
return 0;
err2:
err_scan:
iounmap(cmx270_nand_io);
err1:
err_ioremap:
kfree(cmx270_nand_mtd);
err_kzalloc:
gpio_free(GPIO_NAND_RB);
err_gpio_request:
gpio_free(GPIO_NAND_CS);
return ret;
......@@ -255,6 +267,9 @@ static void cmx270_cleanup(void)
/* Release resources, unregister device */
nand_release(cmx270_nand_mtd);
gpio_free(GPIO_NAND_RB);
gpio_free(GPIO_NAND_CS);
iounmap(cmx270_nand_io);
/* Free the MTD device structure */
......
......@@ -5,83 +5,60 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Compulab Ltd., 2003, 2007
* Compulab Ltd., 2003, 2007, 2008
* Mike Rapoport <mike@compulab.co.il>
*
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <pcmcia/ss.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/cm-x270.h>
#include "soc_common.h"
#define GPIO_PCMCIA_S0_CD_VALID (84)
#define GPIO_PCMCIA_S0_RDYINT (82)
#define GPIO_PCMCIA_RESET (53)
#define PCMCIA_S0_CD_VALID IRQ_GPIO(GPIO_PCMCIA_S0_CD_VALID)
#define PCMCIA_S0_RDYINT IRQ_GPIO(GPIO_PCMCIA_S0_RDYINT)
static struct pcmcia_irqs irqs[] = {
{ 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
{ 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
};
static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
GPIO_bit(GPIO49_nPWE) |
GPIO_bit(GPIO50_nPIOR) |
GPIO_bit(GPIO51_nPIOW) |
GPIO_bit(GPIO85_nPCE_1) |
GPIO_bit(GPIO54_nPCE_2);
pxa_gpio_mode(GPIO48_nPOE_MD);
pxa_gpio_mode(GPIO49_nPWE_MD);
pxa_gpio_mode(GPIO50_nPIOR_MD);
pxa_gpio_mode(GPIO51_nPIOW_MD);
pxa_gpio_mode(GPIO85_nPCE_1_MD);
pxa_gpio_mode(GPIO54_nPCE_2_MD);
pxa_gpio_mode(GPIO55_nPREG_MD);
pxa_gpio_mode(GPIO56_nPWAIT_MD);
pxa_gpio_mode(GPIO57_nIOIS16_MD);
/* Reset signal */
pxa_gpio_mode(GPIO53_nPCE_2 | GPIO_OUT);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
/* irq's for slots: */
set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
int ret = gpio_request(GPIO_PCMCIA_RESET, "PCCard reset");
if (ret)
return ret;
gpio_direction_output(GPIO_PCMCIA_RESET, 0);
skt->irq = PCMCIA_S0_RDYINT;
ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
if (!ret)
gpio_free(GPIO_PCMCIA_RESET);
return ret;
}
static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
{
soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
gpio_free(GPIO_PCMCIA_RESET);
}
static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
struct pcmcia_state *state)
{
state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
state->ready = (PCC_READY(skt->nr) == 0) ? 0 : 1;
state->detect = (gpio_get_value(GPIO_PCMCIA_S0_CD_VALID) == 0) ? 1 : 0;
state->ready = (gpio_get_value(GPIO_PCMCIA_S0_RDYINT) == 0) ? 0 : 1;
state->bvd1 = 1;
state->bvd2 = 1;
state->vs_3v = 0;
......@@ -93,32 +70,16 @@ static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
const socket_state_t *state)
{
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
switch (skt->nr) {
case 0:
if (state->flags & SS_RESET) {
GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
udelay(10);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
}
break;
case 1:
if (state->flags & SS_RESET) {
GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
gpio_set_value(GPIO_PCMCIA_RESET, 1);
udelay(10);
GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
gpio_set_value(GPIO_PCMCIA_RESET, 0);
}
break;
}
pxa_gpio_mode(GPIO49_nPWE_MD);
return 0;
}
......@@ -139,7 +100,7 @@ static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
.configure_socket = cmx270_pcmcia_configure_socket,
.socket_init = cmx270_pcmcia_socket_init,
.socket_suspend = cmx270_pcmcia_socket_suspend,
.nr = 2,
.nr = 1,
};
static struct platform_device *cmx270_pcmcia_device;
......
/*
* linux/include/asm/arch-pxa/cm-x270.h
*
* Copyright Compulab Ltd., 2003, 2007
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* CM-x270 device physical addresses */
#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
#define MARATHON_PHYS (PXA_CS2_PHYS)
#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
/* Statically mapped regions */
#define CMX270_VIRT_BASE (0xe8000000)
#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
/* GPIO related definitions */
#define GPIO_IT8152_IRQ (22)
#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
#define PME_IRQ IRQ_GPIO(0)
#define CMX270_IDE_IRQ IRQ_GPIO(100)
#define CMX270_GPIRQ1 IRQ_GPIO(101)
#define CMX270_TOUCHIRQ IRQ_GPIO(96)
#define CMX270_ETHIRQ IRQ_GPIO(10)
#define CMX270_GFXIRQ IRQ_GPIO(95)
#define CMX270_NANDIRQ IRQ_GPIO(89)
#define CMX270_MMC_IRQ IRQ_GPIO(83)
/* PCMCIA related definitions */
#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
#define PCMCIA_S1_RDYINT IRQ_GPIO(81)