Commit a693f187 authored by Tomas Winkler's avatar Tomas Winkler Committed by John W. Linville

iwlwifi: define ANA_PLL values in iwl-csr.h

This patch defines ANA_PLL values in iwl-csr.h
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fe07aa7a
......@@ -1229,7 +1229,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
iwl3945_power_init_handle(priv);
spin_lock_irqsave(&priv->lock, flags);
iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
......
......@@ -95,8 +95,7 @@
#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
#define CSR_LED_REG (CSR_BASE+0x094)
/* Analog phase-lock-loop configuration (3945 only)
* Set bit 24. */
/* Analog phase-lock-loop configuration */
#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
/*
* Indicates hardware rev, to determine CCK backoff for txpower calculation.
......@@ -219,6 +218,10 @@
#define CSR_LED_REG_TRUN_ON (0x78)
#define CSR_LED_REG_TRUN_OFF (0x38)
/* ANA_PLL */
#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE (0x400)
/*
......
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