Commit a3dddd56 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] War on whitespace: cleanup initial spaces followed by tabs.


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 59b3e8e9
......@@ -214,7 +214,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
if ( NULL != p )
{
memcpy(p, dev, sizeof(dbdev_tab_t));
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
......@@ -260,7 +260,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
(stp->dev_flags & DEV_FLAGS_ANYUSE)) {
/* Got source */
/* Got source */
stp->dev_flags |= DEV_FLAGS_INUSE;
if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
(dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
......
......@@ -174,7 +174,7 @@ int request_au1000_dma(int dev_id, const char *dev_str,
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
return -EINVAL;
#endif
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
......
......@@ -264,7 +264,7 @@ static struct resource smc91x_resources[] = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
......@@ -288,7 +288,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
&au1xxx_mmc_device,
#endif
#ifdef CONFIG_MIPS_DB1200
&smc91x_device,
&smc91x_device,
#endif
};
......
......@@ -90,7 +90,7 @@ void __init plat_setup(void)
else {
/* Clear to obtain best system bus performance */
clear_c0_config(1<<19); /* Clear Config[OD] */
}
}
argptr = prom_getcmdline();
......
......@@ -359,7 +359,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void)
: "hi", "lo", GCC_REG_ACCUM);
/*
* Due to possible jiffies inconsistencies, we need to check
* Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
......
......@@ -45,7 +45,7 @@ static inline void pmax_setup_memory_region(void)
*/
for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE;
mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000;
memory_page += CHUNK_SIZE) {
memory_page += CHUNK_SIZE) {
dummy = *memory_page;
}
memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
......
......@@ -248,17 +248,17 @@ loc_call: /*
and t2,s1
sh t2,JAZZ_IO_IRQ_ENABLE
nor s1,zero,s1
nor s1,zero,s1
jal do_IRQ
/*
* Reenable interrupt
*/
/*
* Reenable interrupt
*/
lhu t2,JAZZ_IO_IRQ_ENABLE
or t2,s1
or t2,s1
sh t2,JAZZ_IO_IRQ_ENABLE
j ret_from_irq
j ret_from_irq
/*
* "Jump extender" to reach spurious_interrupt
......
......@@ -291,7 +291,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
* for documentation. Commented out because it shares
* it's c0_prid id number with the TX3900.
*/
c->cputype = CPU_R4650;
c->cputype = CPU_R4650;
c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
c->tlbsize = 48;
......@@ -604,7 +604,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
case PRID_IMP_AU1_REV2:
switch ((c->processor_id >> 24) & 0xff) {
case 0:
c->cputype = CPU_AU1000;
c->cputype = CPU_AU1000;
break;
case 1:
c->cputype = CPU_AU1500;
......@@ -705,7 +705,7 @@ __init void cpu_probe(void)
break;
case PRID_COMP_PHILIPS:
cpu_probe_philips(c);
break;
break;
default:
c->cputype = CPU_UNKNOWN;
}
......
......@@ -41,7 +41,7 @@
*/
.align 5
NESTED(trap_low, GDB_FR_SIZE, sp)
.set noat
.set noat
.set noreorder
mfc0 k0, CP0_STATUS
......
......@@ -166,11 +166,11 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
sp = regs->regs[29];
/*
* FPU emulator may have it's own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/
sp -= 32;
* FPU emulator may have it's own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/
sp -= 32;
/* This is the X/Open sanctioned signal stack switching. */
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
......
......@@ -624,11 +624,11 @@ static inline void __user *get_sigframe(struct k_sigaction *ka,
sp = regs->regs[29];
/*
* FPU emulator may have it's own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/
sp -= 32;
* FPU emulator may have it's own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/
sp -= 32;
/* This is the X/Open sanctioned signal stack switching. */
if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0))
......
......@@ -576,7 +576,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
}
#endif
/*
* Unimplemented operation exception. If we've got the full
* Unimplemented operation exception. If we've got the full
* software emulator on-board, let's use it...
*
* Force FPU to dump state into task/thread context. We're
......
......@@ -16,7 +16,8 @@ SECTIONS
_image_start = ADDR(.data);
_image_size = SIZEOF(.data);
.other : {
*(.*)
.other :
{
*(.*)
}
}
......@@ -98,7 +98,7 @@
and s0, s1
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
.set mips32
.set mips32
clz a0, s0
.set mips0
negu a0
......
......@@ -96,7 +96,7 @@
andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
#else
beq a0, zero, 1f # delay slot, check hw3 interrupt
andi a0, s0, CAUSEF_IP5
andi a0, s0, CAUSEF_IP5
#endif
/* Wheee, combined hardware level zero interrupt. */
......
......@@ -42,7 +42,7 @@
and s0, s1
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
.set mips32
.set mips32
clz a0, s0
.set mips0
negu a0
......
......@@ -115,7 +115,7 @@ void prom_prepare_cpus(unsigned int max_cpus)
#ifdef CONFIG_MIPS_MT_SMTC
void mipsmt_prepare_cpus(int c);
/*
* As noted above, we can assume a single CPU for now
* As noted above, we can assume a single CPU for now
* but it may be multithreaded.
*/
......
......@@ -129,7 +129,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
"sb\t$0, 0x014(%0)\n\t"
"sb\t$0, 0x018(%0)\n\t"
"sb\t$0, 0x01c(%0)\n\t"
"sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x024(%0)\n\t"
"sb\t$0, 0x028(%0)\n\t"
"sb\t$0, 0x02c(%0)\n\t"
......@@ -145,7 +145,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
"sb\t$0, 0x054(%0)\n\t"
"sb\t$0, 0x058(%0)\n\t"
"sb\t$0, 0x05c(%0)\n\t"
"sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x064(%0)\n\t"
"sb\t$0, 0x068(%0)\n\t"
"sb\t$0, 0x06c(%0)\n\t"
......@@ -182,31 +182,31 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
"sb\t$0, 0x004(%0)\n\t"
"sb\t$0, 0x008(%0)\n\t"
"sb\t$0, 0x00c(%0)\n\t"
"sb\t$0, 0x010(%0)\n\t"
"sb\t$0, 0x010(%0)\n\t"
"sb\t$0, 0x014(%0)\n\t"
"sb\t$0, 0x018(%0)\n\t"
"sb\t$0, 0x01c(%0)\n\t"
"sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x020(%0)\n\t"
"sb\t$0, 0x024(%0)\n\t"
"sb\t$0, 0x028(%0)\n\t"
"sb\t$0, 0x02c(%0)\n\t"
"sb\t$0, 0x030(%0)\n\t"
"sb\t$0, 0x030(%0)\n\t"
"sb\t$0, 0x034(%0)\n\t"
"sb\t$0, 0x038(%0)\n\t"
"sb\t$0, 0x03c(%0)\n\t"
"sb\t$0, 0x040(%0)\n\t"
"sb\t$0, 0x040(%0)\n\t"
"sb\t$0, 0x044(%0)\n\t"
"sb\t$0, 0x048(%0)\n\t"
"sb\t$0, 0x04c(%0)\n\t"
"sb\t$0, 0x050(%0)\n\t"
"sb\t$0, 0x050(%0)\n\t"
"sb\t$0, 0x054(%0)\n\t"
"sb\t$0, 0x058(%0)\n\t"
"sb\t$0, 0x05c(%0)\n\t"
"sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x060(%0)\n\t"
"sb\t$0, 0x064(%0)\n\t"
"sb\t$0, 0x068(%0)\n\t"
"sb\t$0, 0x06c(%0)\n\t"
"sb\t$0, 0x070(%0)\n\t"
"sb\t$0, 0x070(%0)\n\t"
"sb\t$0, 0x074(%0)\n\t"
"sb\t$0, 0x078(%0)\n\t"
"sb\t$0, 0x07c(%0)\n\t"
......
......@@ -32,7 +32,7 @@ void momenco_jaguar_restart(char *command)
#else
void *nvram = (void*) 0xfc807000;
#endif
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
......
......@@ -461,7 +461,7 @@ void __init plat_setup(void)
unsigned int tbControl;
tbControl =
0 << 26 | /* post trigger delay 0 */
0x2 << 16 | /* sequential trace mode */
0x2 << 16 | /* sequential trace mode */
// 0x0 << 16 | /* non-sequential trace mode */
// 0xf << 4 | /* watchpoints disabled */
2 << 2 | /* armed */
......
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