Commit a3a0f8c8 authored by David VomLehn's avatar David VomLehn Committed by Ralf Baechle

MIPS: PowerTV: Base files for Cisco PowerTV platform

Add the Cisco Powertv cable settop box to the MIPS tree. This platform is
based on a MIPS 24Kc processor with various devices integrated on the same
ASIC. There are multiple models of this box, with differing configuration
but the same kernel runs across the product line.
Signed-off-by: default avatarDavid VomLehn <dvomlehn@cisco.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/132/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 13e79b46
......@@ -338,6 +338,24 @@ config PMC_YOSEMITE
Yosemite is an evaluation board for the RM9000x2 processor
manufactured by PMC-Sierra.
config POWERTV
bool "Cisco PowerTV"
select BOOT_ELF32
select CEVT_R4K
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CSRC_POWERTV
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select USB_OHCI_LITTLE_ENDIAN
help
This enables support for the Cisco PowerTV Platform.
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select ARC
......@@ -683,6 +701,7 @@ source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/powertv/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
......@@ -782,6 +801,9 @@ config CSRC_BCM1480
config CSRC_IOASIC
bool
config CSRC_POWERTV
bool
config CSRC_R4K_LIB
bool
......
......@@ -444,6 +444,13 @@ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
#
# Cisco PowerTV Platform
#
core-$(CONFIG_POWERTV) += arch/mips/powertv/
cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
load-$(CONFIG_POWERTV) += 0xffffffff90800000
#
# SGI IP22 (Indy/Indigo2)
#
......
This diff is collapsed.
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_ASIC_H
#define _ASM_MACH_POWERTV_ASIC_H
#include <linux/ioport.h>
#include <asm/mach-powertv/asic_regs.h>
#define DVR_CAPABLE (1<<0)
#define PCIE_CAPABLE (1<<1)
#define FFS_CAPABLE (1<<2)
#define DISPLAY_CAPABLE (1<<3)
/* Platform Family types
* For compitability, the new value must be added in the end */
enum family_type {
FAMILY_8500,
FAMILY_8500RNG,
FAMILY_4500,
FAMILY_1500,
FAMILY_8600,
FAMILY_4600,
FAMILY_4600VZA,
FAMILY_8600VZB,
FAMILY_1500VZE,
FAMILY_1500VZF,
FAMILIES
};
/* Register maps for each ASIC */
extern const struct register_map calliope_register_map;
extern const struct register_map cronus_register_map;
extern const struct register_map zeus_register_map;
extern struct resource dvr_cronus_resources[];
extern struct resource dvr_zeus_resources[];
extern struct resource non_dvr_calliope_resources[];
extern struct resource non_dvr_cronus_resources[];
extern struct resource non_dvr_cronuslite_resources[];
extern struct resource non_dvr_vz_calliope_resources[];
extern struct resource non_dvr_vze_calliope_resources[];
extern struct resource non_dvr_vzf_calliope_resources[];
extern struct resource non_dvr_zeus_resources[];
extern void powertv_platform_init(void);
extern void platform_alloc_bootmem(void);
extern enum asic_type platform_get_asic(void);
extern enum family_type platform_get_family(void);
extern int platform_supports_dvr(void);
extern int platform_supports_ffs(void);
extern int platform_supports_pcie(void);
extern int platform_supports_display(void);
extern void configure_platform(void);
extern void platform_configure_usb_ehci(void);
extern void platform_unconfigure_usb_ehci(void);
extern void platform_configure_usb_ohci(void);
extern void platform_unconfigure_usb_ohci(void);
/* Platform Resources */
#define ASIC_RESOURCE_GET_EXISTS 1
extern struct resource *asic_resource_get(const char *name);
extern void platform_release_memory(void *baddr, int size);
/* Reboot Cause */
extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
extern void set_locked_reboot_cause(char code, unsigned int data,
unsigned int data2);
enum sys_reboot_type {
sys_unknown_reboot = 0x00, /* Unknown reboot cause */
sys_davic_change = 0x01, /* Reboot due to change in DAVIC
* mode */
sys_user_reboot = 0x02, /* Reboot initiated by user */
sys_system_reboot = 0x03, /* Reboot initiated by OS */
sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
sys_silent_reboot = 0x05, /* Silent reboot */
sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
sys_power_up_reboot = 0x07, /* Power on bootup. Older
* drivers may report as
* userReboot. */
sys_code_change = 0x08, /* Reboot to take code change.
* Older drivers may report as
* userReboot. */
sys_hardware_reset = 0x09, /* HW watchdog or front-panel
* reset button reset. Older
* drivers may report as
* userReboot. */
sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
};
#endif /* _ASM_MACH_POWERTV_ASIC_H */
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_MACH_POWERTV_ASIC_H_
#define __ASM_MACH_POWERTV_ASIC_H_
#include <linux/io.h>
/* ASIC types */
enum asic_type {
ASIC_UNKNOWN,
ASIC_ZEUS,
ASIC_CALLIOPE,
ASIC_CRONUS,
ASIC_CRONUSLITE,
ASICS
};
/* hardcoded values read from Chip Version registers */
#define CRONUS_10 0x0B4C1C20
#define CRONUS_11 0x0B4C1C21
#define CRONUSLITE_10 0x0B4C1C40
#define NAND_FLASH_BASE 0x03000000
#define ZEUS_IO_BASE 0x09000000
#define CALLIOPE_IO_BASE 0x08000000
#define CRONUS_IO_BASE 0x09000000
#define ASIC_IO_SIZE 0x01000000
/* Definitions for backward compatibility */
#define UART1_INTSTAT uart1_intstat
#define UART1_INTEN uart1_inten
#define UART1_CONFIG1 uart1_config1
#define UART1_CONFIG2 uart1_config2
#define UART1_DIVISORHI uart1_divisorhi
#define UART1_DIVISORLO uart1_divisorlo
#define UART1_DATA uart1_data
#define UART1_STATUS uart1_status
/* ASIC register enumeration */
struct register_map {
u32 eic_slow0_strt_add;
u32 eic_cfg_bits;
u32 eic_ready_status;
u32 chipver3;
u32 chipver2;
u32 chipver1;
u32 chipver0;
u32 uart1_intstat;
u32 uart1_inten;
u32 uart1_config1;
u32 uart1_config2;
u32 uart1_divisorhi;
u32 uart1_divisorlo;
u32 uart1_data;
u32 uart1_status;
u32 int_stat_3;
u32 int_stat_2;
u32 int_stat_1;
u32 int_stat_0;
u32 int_config;
u32 int_int_scan;
u32 ien_int_3;
u32 ien_int_2;
u32 ien_int_1;
u32 ien_int_0;
u32 int_level_3_3;
u32 int_level_3_2;
u32 int_level_3_1;
u32 int_level_3_0;
u32 int_level_2_3;
u32 int_level_2_2;
u32 int_level_2_1;
u32 int_level_2_0;
u32 int_level_1_3;
u32 int_level_1_2;
u32 int_level_1_1;
u32 int_level_1_0;
u32 int_level_0_3;
u32 int_level_0_2;
u32 int_level_0_1;
u32 int_level_0_0;
u32 int_docsis_en;
u32 mips_pll_setup;
u32 usb_fs;
u32 test_bus;
u32 crt_spare;
u32 usb2_ohci_int_mask;
u32 usb2_strap;
u32 ehci_hcapbase;
u32 ohci_hc_revision;
u32 bcm1_bs_lmi_steer;
u32 usb2_control;
u32 usb2_stbus_obc;
u32 usb2_stbus_mess_size;
u32 usb2_stbus_chunk_size;
u32 pcie_regs;
u32 tim_ch;
u32 tim_cl;
u32 gpio_dout;
u32 gpio_din;
u32 gpio_dir;
u32 watchdog;
u32 front_panel;
u32 register_maps;
};
extern enum asic_type asic;
extern const struct register_map *register_map;
extern unsigned long asic_phy_base; /* Physical address of ASIC */
extern unsigned long asic_base; /* Virtual address of ASIC */
/*
* Macros to interface to registers through their ioremapped address
* asic_reg_offset Returns the offset of a given register from the start
* of the ASIC address space
* asic_reg_phys_addr Returns the physical address of the given register
* asic_reg_addr Returns the iomapped virtual address of the given
* register.
*/
#define asic_reg_offset(x) (register_map->x)
#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
#define asic_reg_addr(x) \
((unsigned int *) (asic_base + asic_reg_offset(x)))
/*
* The asic_reg macro is gone. It should be replaced by either asic_read or
* asic_write, as appropriate.
*/
#define asic_read(x) readl(asic_reg_addr(x))
#define asic_write(v, x) writel(v, asic_reg_addr(x))
extern void asic_irq_init(void);
#endif
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Version from mach-generic modified to support PowerTV port
* Portions Copyright (C) 2009 Cisco Systems, Inc.
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
#include <linux/sched.h>
#include <linux/version.h>
#include <linux/device.h>
#include <asm/mach-powertv/asic.h>
static inline bool is_kseg2(void *addr)
{
return (unsigned long)addr >= KSEG2;
}
static inline unsigned long virt_to_phys_from_pte(void *addr)
{
pgd_t *pgd;
pud_t *pud;
pmd_t *pmd;
pte_t *ptep, pte;
unsigned long virt_addr = (unsigned long)addr;
unsigned long phys_addr = 0UL;
/* get the page global directory. */
pgd = pgd_offset_k(virt_addr);
if (!pgd_none(*pgd)) {
/* get the page upper directory */
pud = pud_offset(pgd, virt_addr);
if (!pud_none(*pud)) {
/* get the page middle directory */
pmd = pmd_offset(pud, virt_addr);
if (!pmd_none(*pmd)) {
/* get a pointer to the page table entry */
ptep = pte_offset(pmd, virt_addr);
pte = *ptep;
/* check for a valid page */
if (pte_present(pte)) {
/* get the physical address the page is
* refering to */
phys_addr = (unsigned long)
page_to_phys(pte_page(pte));
/* add the offset within the page */
phys_addr |= (virt_addr & ~PAGE_MASK);
}
}
}
}
return phys_addr;
}
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
if (is_kseg2(addr))
return phys_to_bus(virt_to_phys_from_pte(addr));
else
return phys_to_bus(virt_to_phys(addr));
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
return phys_to_bus(page_to_phys(page));
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return bus_to_phys(dma_addr);
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
return;
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
}
#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
#define _ASM_MACH_POWERTV_INTERRUPTS_H_
/*
* Defines for all of the interrupt lines
*/
/* Definitions for backward compatibility */
#define kIrq_Uart1 irq_uart1
#define ibase 0
/*------------- Register: int_stat_3 */
/* 126 unused (bit 31) */
#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
* Interrupt */
#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
* -- Ored by glue logic inside
* SPARC ILC (see
* INT_MEM_PROT_STAT, below,
* for individual interrupts)
*/
/* 118 unused (bit 22) */
#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
* glue logic inside SPARC ILC
* (see INT_SBAG_STAT, below,
* for individual interrupts) */
#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
/* 114 unused (bit 18) */
#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
* Ored by glue logic inside
* SPARC ILC (see
* INT_MAILBOX_STAT, below, for
* individual interrupts) */
#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */
#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */
#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
* Interrupt */
#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
* Interrupt */
#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
* Interrupt */
#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
* Interrupt */
#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
* Interrupt */
#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
* Interrupt */
#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
* Interrupt */
#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
/*------------- Register: int_stat_2 */
#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
#define irq_timer2 (ibase+93) /* Programmable Timer
* Interrupt 2 */
#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
#define irq_sata (ibase+87) /* SATA 1 Interrupt */
#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
#define irq_dtcp (ibase+86) /* DTCP Interrupt */
#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
/* 84 unused (bit 20) */
/* 83 unused (bit 19) */
/* 82 unused (bit 18) */
#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
#define irq_uart2 (ibase+80) /* UART2 Interrupt */
#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
* Host module) */
#define irq_pod (ibase+78) /* POD Interrupt */
#define irq_slave_usb (ibase+77) /* Slave USB */
#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
/* 67 unused (bit 03) */
/* 66 unused (bit 02) */
/* 65 unused (bit 01) */
/* 64 unused (bit 00) */
/*------------- Register: int_stat_1 */
/* 63 unused (bit 31) */
/* 62 unused (bit 30) */
/* 61 unused (bit 29) */
/* 60 unused (bit 28) */
/* 59 unused (bit 27) */
/* 58 unused (bit 26) */
/* 57 unused (bit 25) */
/* 56 unused (bit 24) */
#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
* Interrupt */
#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
* Interrupt */
#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
* Interrupt */
#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
* Interrupt */
#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
* Interrupt */
#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
* Interrupt */
#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
* Interrupt */
#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
* Interrupt */
#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
* Interrupt */
#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
* (Chans 63-32) */
#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
* (Chans 31-0) */
#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
* (Chans 63-32) */
#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
* (Chans 31-0) */
#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
* Interrupt */
#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
* Interrupt */
#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */