Commit 9f5dc91b authored by Nishanth Menon's avatar Nishanth Menon
Browse files

ARM: OMAP5: powerdomain data: fix powerdomain powerstate



Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarKevin Hilman <khilman@linaro.org>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent cafc8cb5
...@@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = { ...@@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = {
.prcm_offs = OMAP54XX_PRM_CORE_INST, .prcm_offs = OMAP54XX_PRM_CORE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION, .prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON, .pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 5, .banks = 5,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
...@@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = { ...@@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = {
.voltdm = { .name = "mpu" }, .voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
...@@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = { ...@@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = {
.voltdm = { .name = "mpu" }, .voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
...@@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = { ...@@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = {
.prcm_offs = OMAP54XX_PRM_MPU_INST, .prcm_offs = OMAP54XX_PRM_MPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION, .prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON, .pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 2, .banks = 2,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment