Commit 9e290a19 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Remove execution hazard barriers for Octeon.



The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 41f0e4d0
......@@ -47,6 +47,7 @@
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 1
#define cpu_has_mips_r2_exec_hazard 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
......
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