Commit 9ddfd929 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
  MIPS: O32: Fix ppoll
  MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
  MIPS: Alchemy: Fix hang with high-frequency edge interrupts
  MIPS: TXx9: Fix spi-baseclk value
  MIPS: bcm63xx: Set the correct BCM3302 CPU name
  MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
  MIPS: Avoid potential hazard on Context register
  MIPS: Octeon: Use lockless interrupt controller operations when possible.
  MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
  MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
  MIPS: SMTC: Avoid queing multiple reschedule IPIs
  MIPS: GCMP: Avoid accessing registers when they are not present
  MIPS: GIC: Random fixes and enhancements.
  MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
  MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
  MIPS: SPRAM: Clean up support code a little
  MIPS: 1004K: Enable SPRAM support.
  MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
  MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
  MIPS: MTI: Fix accesses to device registers on MIPS boards
  ...
parents 38dc6345 049a31af
......@@ -1012,9 +1012,9 @@ config BOOT_ELF32
config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION || MIKROTIK_RB532
default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
default "6" if MIPS_CPU_SCACHE
default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
default "4" if PMC_MSP4200_EVAL
default "5"
config HAVE_STD_PC_SERIAL_PORT
......
......@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr)
au_sync();
}
static void au1x_ic0_maskack(unsigned int irq_nr)
{
unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
au_writel(1 << bit, IC0_WAKECLR);
au_writel(1 << bit, IC0_MASKCLR);
au_writel(1 << bit, IC0_RISINGCLR);
au_writel(1 << bit, IC0_FALLINGCLR);
au_sync();
}
static void au1x_ic1_maskack(unsigned int irq_nr)
{
unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
au_writel(1 << bit, IC1_WAKECLR);
au_writel(1 << bit, IC1_MASKCLR);
au_writel(1 << bit, IC1_RISINGCLR);
au_writel(1 << bit, IC1_FALLINGCLR);
au_sync();
}
static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
{
unsigned int bit = irq - AU1000_INTC1_INT_BASE;
......@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
/*
* irq_chips for both ICs; this way the mask handlers can be
* as short as possible.
*
* NOTE: the ->ack() callback is used by the handle_edge_irq
* flowhandler only, the ->mask_ack() one by handle_level_irq,
* so no need for an irq_chip for each type of irq (level/edge).
*/
static struct irq_chip au1x_ic0_chip = {
.name = "Alchemy-IC0",
.ack = au1x_ic0_ack, /* edge */
.ack = au1x_ic0_ack,
.mask = au1x_ic0_mask,
.mask_ack = au1x_ic0_mask, /* level */
.mask_ack = au1x_ic0_maskack,
.unmask = au1x_ic0_unmask,
.set_type = au1x_ic_settype,
};
static struct irq_chip au1x_ic1_chip = {
.name = "Alchemy-IC1",
.ack = au1x_ic1_ack, /* edge */
.ack = au1x_ic1_ack,
.mask = au1x_ic1_mask,
.mask_ack = au1x_ic1_mask, /* level */
.mask_ack = au1x_ic1_maskack,
.unmask = au1x_ic1_unmask,
.set_type = au1x_ic_settype,
.set_wake = au1x_ic1_setwake,
......
......@@ -69,6 +69,7 @@ void __init board_setup(void)
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
board_pci_idsel = mtx1_pci_idsel;
#endif
/* Initialize sys_pinfunc */
......@@ -85,8 +86,6 @@ void __init board_setup(void)
alchemy_gpio_direction_output(211, 1); /* green on */
alchemy_gpio_direction_output(212, 0); /* red off */
board_pci_idsel = mtx1_pci_idsel;
printk(KERN_INFO "4G Systems MTX-1 Board\n");
}
......
......@@ -503,6 +503,7 @@ static int __init ar7_register_devices(void)
{
u16 chip_id;
int res;
u32 *bootcr, val;
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port[2];
......@@ -595,7 +596,13 @@ static int __init ar7_register_devices(void)
ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
res = platform_device_register(&ar7_wdt);
bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
val = *bootcr;
iounmap(bootcr);
/* Register watchdog only if enabled in hardware */
if (val & AR7_WDT_HW_ENA)
res = platform_device_register(&ar7_wdt);
return res;
}
......
obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o
dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
......
......@@ -24,7 +24,6 @@
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_dev_pcmcia.h>
#include <bcm63xx_dev_uart.h>
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
......@@ -794,8 +793,6 @@ int __init board_register_devices(void)
{
u32 val;
bcm63xx_uart_register();
if (board.has_pccard)
bcm63xx_pcmcia_register();
......
......@@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <asm/cpu-info.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
......@@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void)
{
unsigned int tmp, expected_cpu_id;
struct cpuinfo_mips *c = &current_cpu_data;
unsigned int cpu = smp_processor_id();
/* soc registers location depends on cpu type */
expected_cpu_id = 0;
......@@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void)
* BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
*/
case CPU_BCM3302:
__cpu_name[cpu] = "Broadcom BCM6338";
expected_cpu_id = BCM6338_CPU_ID;
bcm63xx_regs_base = bcm96338_regs_base;
bcm63xx_irqs = bcm96338_irqs;
......
......@@ -10,7 +10,6 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_uart.h>
static struct resource uart_resources[] = {
{
......@@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void)
uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
return platform_device_register(&bcm63xx_uart_device);
}
arch_initcall(bcm63xx_uart_register);
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
static struct resource wdt_resources[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
};
static struct platform_device bcm63xx_wdt_device = {
.name = "bcm63xx-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
int __init bcm63xx_wdt_register(void)
{
wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT);
wdt_resources[0].end = wdt_resources[0].start;
wdt_resources[0].end += RSET_WDT_SIZE - 1;
return platform_device_register(&bcm63xx_wdt_device);
}
arch_initcall(bcm63xx_wdt_register);
......@@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void)
bcm6348_a1_reboot();
printk(KERN_INFO "triggering watchdog soft-reset...\n");
bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
reg |= SYS_PLL_SOFT_RESET;
bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
while (1)
;
}
......
......@@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
DEFINE_SPINLOCK(octeon_irq_msi_lock);
static int octeon_coreid_for_cpu(int cpu)
{
#ifdef CONFIG_SMP
return cpu_logical_map(cpu);
#else
return cvmx_get_core_num();
#endif
}
static void octeon_irq_core_ack(unsigned int irq)
{
unsigned int bit = irq - OCTEON_IRQ_SW0;
......@@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
unsigned long flags;
uint64_t en0;
#ifdef CONFIG_SMP
int cpu;
write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
for_each_online_cpu(cpu) {
int coreid = cpu_logical_map(cpu);
int coreid = octeon_coreid_for_cpu(cpu);
en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
en0 &= ~(1ull << bit);
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
......@@ -167,26 +175,57 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
*/
cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
#else
int coreid = cvmx_get_core_num();
local_irq_save(flags);
en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
en0 &= ~(1ull << bit);
cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
local_irq_restore(flags);
#endif
}
/*
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu0_enable_v2(unsigned int irq)
{
int index = cvmx_get_core_num() * 2;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
}
/*
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu0_disable_v2(unsigned int irq)
{
int index = cvmx_get_core_num() * 2;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
}
/*
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
{
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
int index;
int cpu;
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2;
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
}
}
#ifdef CONFIG_SMP
static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
{
int cpu;
unsigned long flags;
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
write_lock(&octeon_irq_ciu0_rwlock);
write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
for_each_online_cpu(cpu) {
int coreid = cpu_logical_map(cpu);
int coreid = octeon_coreid_for_cpu(cpu);
uint64_t en0 =
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
if (cpumask_test_cpu(cpu, dest))
......@@ -200,11 +239,45 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
* of them are done.
*/
cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
write_unlock(&octeon_irq_ciu0_rwlock);
write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
return 0;
}
/*
* Set affinity for the irq for chips that have the EN*_W1{S,C}
* registers.
*/
static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
const struct cpumask *dest)
{
int cpu;
int index;
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2;
if (cpumask_test_cpu(cpu, dest))
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
else
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
}
return 0;
}
#endif
/*
* Newer octeon chips have support for lockless CIU operation.
*/
static struct irq_chip octeon_irq_chip_ciu0_v2 = {
.name = "CIU0",
.enable = octeon_irq_ciu0_enable_v2,
.disable = octeon_irq_ciu0_disable_all_v2,
.ack = octeon_irq_ciu0_disable_v2,
.eoi = octeon_irq_ciu0_enable_v2,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu0_set_affinity_v2,
#endif
};
static struct irq_chip octeon_irq_chip_ciu0 = {
.name = "CIU0",
......@@ -269,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
unsigned long flags;
uint64_t en1;
#ifdef CONFIG_SMP
int cpu;
write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
for_each_online_cpu(cpu) {
int coreid = cpu_logical_map(cpu);
int coreid = octeon_coreid_for_cpu(cpu);
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
en1 &= ~(1ull << bit);
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
......@@ -284,26 +356,58 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
*/
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
#else
int coreid = cvmx_get_core_num();
local_irq_save(flags);
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
en1 &= ~(1ull << bit);
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
local_irq_restore(flags);
#endif
}
/*
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu1_enable_v2(unsigned int irq)
{
int index = cvmx_get_core_num() * 2 + 1;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
}
/*
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu1_disable_v2(unsigned int irq)
{
int index = cvmx_get_core_num() * 2 + 1;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
}
/*
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
* registers.
*/
static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
{
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
int index;
int cpu;
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
}
}
#ifdef CONFIG_SMP
static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
static int octeon_irq_ciu1_set_affinity(unsigned int irq,
const struct cpumask *dest)
{
int cpu;
unsigned long flags;
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
write_lock(&octeon_irq_ciu1_rwlock);
write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
for_each_online_cpu(cpu) {
int coreid = cpu_logical_map(cpu);
int coreid = octeon_coreid_for_cpu(cpu);
uint64_t en1 =
cvmx_read_csr(CVMX_CIU_INTX_EN1
(coreid * 2 + 1));
......@@ -318,12 +422,46 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
* of them are done.
*/
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
write_unlock(&octeon_irq_ciu1_rwlock);
write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
return 0;
}
/*
* Set affinity for the irq for chips that have the EN*_W1{S,C}
* registers.
*/
static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
const struct cpumask *dest)
{
int cpu;
int index;
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
for_each_online_cpu(cpu) {
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
if (cpumask_test_cpu(cpu, dest))
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
else
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
}
return 0;
}
#endif
/*
* Newer octeon chips have support for lockless CIU operation.
*/
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
.name = "CIU0",
.enable = octeon_irq_ciu1_enable_v2,
.disable = octeon_irq_ciu1_disable_all_v2,
.ack = octeon_irq_ciu1_disable_v2,
.eoi = octeon_irq_ciu1_enable_v2,
#ifdef CONFIG_SMP
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
#endif
};
static struct irq_chip octeon_irq_chip_ciu1 = {
.name = "CIU1",
.enable = octeon_irq_ciu1_enable,
......@@ -420,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = {
void __init arch_init_irq(void)
{
int irq;
struct irq_chip *chip0;
struct irq_chip *chip1;
#ifdef CONFIG_SMP
/* Set the default affinity to the boot cpu. */
......@@ -430,6 +570,16 @@ void __init arch_init_irq(void)
if (NR_IRQS < OCTEON_IRQ_LAST)
pr_err("octeon_irq_init: NR_IRQS is set too low\n");
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
chip0 = &octeon_irq_chip_ciu0_v2;
chip1 = &octeon_irq_chip_ciu1_v2;
} else {
chip0 = &octeon_irq_chip_ciu0;
chip1 = &octeon_irq_chip_ciu1;
}
/* 0 - 15 reserved for i8259 master and slave controller. */
/* 17 - 23 Mips internal */
......@@ -440,14 +590,12 @@ void __init arch_init_irq(void)
/* 24 - 87 CIU_INT_SUM0 */
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
handle_percpu_irq);
set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
}
/* 88 - 151 CIU_INT_SUM1 */
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
handle_percpu_irq);
set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
}
#ifdef CONFIG_PCI_MSI
......@@ -505,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void)
#ifdef CONFIG_HOTPLUG_CPU
static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
{
unsigned int isset;
#ifdef CONFIG_SMP
int coreid = cpu_logical_map(cpu);
#else
int coreid = cvmx_get_core_num();
#endif
unsigned int isset;
int coreid = octeon_coreid_for_cpu(cpu);
int bit = (irq < OCTEON_IRQ_WDOG0) ?
irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
if (irq < 64) {
isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
(1ull << bit)) >> bit;
......
......@@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action)
cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}
static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
static inline void octeon_send_ipi_mask(const struct cpumask *mask,
unsigned int action)
{
unsigned int i;
for_each_cpu_mask(i, mask)
for_each_cpu_mask(i, *mask)
octeon_send_ipi_single(i, action);
}
......
......@@ -48,9 +48,9 @@ enum fixed_addresses {
#define FIX_N_COLOURS 8
FIX_CMAP_BEGIN,
#ifdef CONFIG_MIPS_MT_SMTC
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
#else
FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
#endif
#ifdef CONFIG_HIGHMEM
/* reserved pte's for temporary kernel mappings */
......
......@@ -19,15 +19,20 @@
#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
/* Offsets to individual GCMP registers from GCMP base */
#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
#define GCMPOFS(block, tag, reg) \
(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
#define GCMPOFSn(block, tag, reg, n) \
(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
/* GCMP register access */
#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
......@@ -49,10 +54,10 @@
#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0
#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1
#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2