Commit 9d56dd3b authored by Paul Mundt's avatar Paul Mundt

sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent a077e916
......@@ -23,7 +23,7 @@
#include <asm/heartbeat.h>
#include <cpu/sh7720.h>
#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL)
#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
/* Prefer cmdline over RedBoot */
static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
......@@ -60,33 +60,33 @@ static void __init setup_chip_select(void)
{
/* CS2: LAN (0x08000000 - 0x0bffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x36db0400, CS2BCR);
__raw_writel(0x36db0400, CS2BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x000003c0, CS2WCR);
__raw_writel(0x000003c0, CS2WCR);
/* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS4BCR);
__raw_writel(0x00000200, CS4BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS4WCR);
__raw_writel(0x00100981, CS4WCR);
/* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5ABCR);
__raw_writel(0x00000200, CS5ABCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5AWCR);
__raw_writel(0x00100981, CS5AWCR);
/* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5BBCR);
__raw_writel(0x00000200, CS5BBCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5BWCR);
__raw_writel(0x00100981, CS5BWCR);
/* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS6ABCR);
__raw_writel(0x00000200, CS6ABCR);
/* (SW:1.5 WR:3 HW:1.5), no ext. wait */
ctrl_outl(0x001009C1, CS6AWCR);
__raw_writel(0x001009C1, CS6AWCR);
}
static void __init setup_port_multiplexing(void)
......@@ -94,71 +94,71 @@ static void __init setup_port_multiplexing(void)
/* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
* A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
*/
ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
/* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
* B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
*/
ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
/* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
* C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
*/
ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
__raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
/* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
* D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
*/
ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
__raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
/* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
* E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
*/
ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
__raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
/* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
* F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
*/
ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
__raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
/* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
* G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
*/
ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
__raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
/* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
* H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
*/
ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
__raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
/* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
* J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
*/
ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
__raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
/* K7 (x); K6 (x); K5 (x); K4 (x);
* K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
*/
ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
__raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
/* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
* L3 TCK; L2 (x); L1 (x); L0 (x);
*/
ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
__raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
/* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
* M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
* M1 CS5B(CAN3_CS); M0 GPI+(nc);
*/
ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
__raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
/* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
* LAN_RESET=off, BUZZER=off, LCD_BL=off
*/
#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
ctrl_outb(0x30, PORT_PMDR);
__raw_writeb(0x30, PORT_PMDR);
#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
ctrl_outb(0xF0, PORT_PMDR);
__raw_writeb(0xF0, PORT_PMDR);
#else
#error Unknown revision of PLATFORM_MP_R2
#endif
......@@ -167,8 +167,8 @@ static void __init setup_port_multiplexing(void)
* P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
* P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
*/
ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
ctrl_outb(0x10, PORT_PPDR);
__raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
__raw_writeb(0x10, PORT_PPDR);
/* R7 A25; R6 A24; R5 A23; R4 A22;
* R3 A21; R2 A20; R1 A19; R0 A0;
......@@ -185,22 +185,22 @@ static void __init setup_port_multiplexing(void)
/* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
* S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
*/
ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
__raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
/* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
* T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
*/
ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
__raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
/* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
* U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
*/
ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
__raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
/* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
* V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
*/
ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
__raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
}
static void __init mpr2_setup(char **cmdline_p)
......@@ -209,24 +209,24 @@ static void __init mpr2_setup(char **cmdline_p)
* /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
* /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
*/
ctrl_outw(0xAABC, PORT_PSELA);
__raw_writew(0xAABC, PORT_PSELA);
/* set Pin Select Register B:
* /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
* LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
*/
ctrl_outw(0x3C00, PORT_PSELB);
__raw_writew(0x3C00, PORT_PSELB);
/* set Pin Select Register C:
* SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
*/
ctrl_outw(0x0000, PORT_PSELC);
__raw_writew(0x0000, PORT_PSELC);
/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
* Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
*/
ctrl_outw(0x0000, PORT_PSELD);
__raw_writew(0x0000, PORT_PSELD);
/* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
ctrl_outw(0x0101, PORT_UTRCTL);
__raw_writew(0x0101, PORT_UTRCTL);
/* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
ctrl_outw(0xA5C0, PORT_UCLKCR_W);
__raw_writew(0xA5C0, PORT_UCLKCR_W);
setup_chip_select();
......
......@@ -89,15 +89,15 @@ static int __init polaris_initialise(void)
printk(KERN_INFO "Configuring Polaris external bus\n");
/* Configure area 5 with 2 wait states */
wcr = ctrl_inw(WCR2);
wcr = __raw_readw(WCR2);
wcr &= (~AREA5_WAIT_CTRL);
wcr |= (WAIT_STATES_10 << 10);
ctrl_outw(wcr, WCR2);
__raw_writew(wcr, WCR2);
/* Configure area 5 for 32-bit access */
bcr_mask = ctrl_inw(BCR2);
bcr_mask = __raw_readw(BCR2);
bcr_mask |= 1 << 10;
ctrl_outw(bcr_mask, BCR2);
__raw_writew(bcr_mask, BCR2);
return platform_add_devices(polaris_devices,
ARRAY_SIZE(polaris_devices));
......@@ -128,13 +128,13 @@ static struct ipr_desc ipr_irq_desc = {
static void __init init_polaris_irq(void)
{
/* Disable all interrupts */
ctrl_outw(0, BCR_ILCRA);
ctrl_outw(0, BCR_ILCRB);
ctrl_outw(0, BCR_ILCRC);
ctrl_outw(0, BCR_ILCRD);
ctrl_outw(0, BCR_ILCRE);
ctrl_outw(0, BCR_ILCRF);
ctrl_outw(0, BCR_ILCRG);
__raw_writew(0, BCR_ILCRA);
__raw_writew(0, BCR_ILCRB);
__raw_writew(0, BCR_ILCRC);
__raw_writew(0, BCR_ILCRD);
__raw_writew(0, BCR_ILCRE);
__raw_writew(0, BCR_ILCRF);
__raw_writew(0, BCR_ILCRG);
register_ipr_controller(&ipr_irq_desc);
}
......
......@@ -17,8 +17,8 @@
static void __init init_shmin_irq(void)
{
ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
__raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
__raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
......
......@@ -159,21 +159,21 @@ static void ap320_wvga_power_on(void *board_data)
msleep(100);
/* ASD AP-320/325 LCD ON */
ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
/* backlight */
gpio_set_value(GPIO_PTS3, 0);
ctrl_outw(0x100, FPGA_BKLREG);
__raw_writew(0x100, FPGA_BKLREG);
}
static void ap320_wvga_power_off(void *board_data)
{
/* backlight */
ctrl_outw(0, FPGA_BKLREG);
__raw_writew(0, FPGA_BKLREG);
gpio_set_value(GPIO_PTS3, 1);
/* ASD AP-320/325 LCD OFF */
ctrl_outw(0, FPGA_LCDREG);
__raw_writew(0, FPGA_LCDREG);
}
static struct sh_mobile_lcdc_info lcdc_info = {
......@@ -595,7 +595,7 @@ static int __init ap325rxa_devices_setup(void)
gpio_request(GPIO_PTZ4, NULL);
gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
/* FLCTL */
gpio_request(GPIO_FN_FCE, NULL);
......@@ -613,9 +613,9 @@ static int __init ap325rxa_devices_setup(void)
gpio_request(GPIO_FN_FWE, NULL);
gpio_request(GPIO_FN_FRB, NULL);
ctrl_outw(0, PORT_HIZCRC);
ctrl_outw(0xFFFF, PORT_DRVCRA);
ctrl_outw(0xFFFF, PORT_DRVCRB);
__raw_writew(0, PORT_HIZCRC);
__raw_writew(0xFFFF, PORT_DRVCRA);
__raw_writew(0xFFFF, PORT_DRVCRB);
platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
......
......@@ -66,9 +66,9 @@ static void enable_cayman_irq(unsigned int irq)
reg = EPLD_MASK_BASE + ((irq / 8) << 2);
bit = 1<<(irq % 8);
local_irq_save(flags);
mask = ctrl_inl(reg);
mask = __raw_readl(reg);
mask |= bit;
ctrl_outl(mask, reg);
__raw_writel(mask, reg);
local_irq_restore(flags);
}
......@@ -83,9 +83,9 @@ void disable_cayman_irq(unsigned int irq)
reg = EPLD_MASK_BASE + ((irq / 8) << 2);
bit = 1<<(irq % 8);
local_irq_save(flags);
mask = ctrl_inl(reg);
mask = __raw_readl(reg);
mask &= ~bit;
ctrl_outl(mask, reg);
__raw_writel(mask, reg);
local_irq_restore(flags);
}
......@@ -109,8 +109,8 @@ int cayman_irq_demux(int evt)
unsigned long status;
int i;
status = ctrl_inl(EPLD_STATUS_BASE) &
ctrl_inl(EPLD_MASK_BASE) & 0xff;
status = __raw_readl(EPLD_STATUS_BASE) &
__raw_readl(EPLD_MASK_BASE) & 0xff;
if (status == 0) {
irq = -1;
} else {
......@@ -126,8 +126,8 @@ int cayman_irq_demux(int evt)
unsigned long status;
int i;
status = ctrl_inl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
ctrl_inl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
__raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
if (status == 0) {
irq = -1;
} else {
......
......@@ -35,11 +35,11 @@ static void aica_rtc_gettimeofday(struct timespec *ts)
unsigned long val1, val2;
do {
val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
} while (val1 != val2);
ts->tv_sec = val1 - TWENTY_YEARS;
......@@ -60,14 +60,14 @@ static int aica_rtc_settimeofday(const time_t secs)
unsigned long adj = secs + TWENTY_YEARS;
do {
ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L);
__raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
__raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
} while (val1 != val2);
return 0;
......
......@@ -696,13 +696,13 @@ static struct platform_device camera_devices[] = {
#define FCLKBCR 0xa415000c
static void fsimck_init(struct clk *clk)
{
u32 status = ctrl_inl(clk->enable_reg);
u32 status = __raw_readl(clk->enable_reg);
/* use external clock */
status &= ~0x000000ff;
status |= 0x00000080;
ctrl_outl(status, clk->enable_reg);
__raw_writel(status, clk->enable_reg);
}
static struct clk_ops fsimck_clk_ops = {
......@@ -853,7 +853,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTG1, 0);
gpio_direction_output(GPIO_PTG2, 0);
gpio_direction_output(GPIO_PTG3, 0);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
__raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
/* enable SH-Eth */
gpio_request(GPIO_PTA1, NULL);
......@@ -873,16 +873,16 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_LNKSTA, NULL);
/* enable USB */
ctrl_outw(0x0000, 0xA4D80000);
ctrl_outw(0x0000, 0xA4D90000);
__raw_writew(0x0000, 0xA4D80000);
__raw_writew(0x0000, 0xA4D90000);
gpio_request(GPIO_PTB3, NULL);
gpio_request(GPIO_PTB4, NULL);
gpio_request(GPIO_PTB5, NULL);
gpio_direction_input(GPIO_PTB3);
gpio_direction_output(GPIO_PTB4, 0);
gpio_direction_output(GPIO_PTB5, 0);
ctrl_outw(0x0600, 0xa40501d4);
ctrl_outw(0x0600, 0xa4050192);
__raw_writew(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa4050192);
if (gpio_get_value(GPIO_PTB3)) {
printk(KERN_INFO "USB1 function is selected\n");
......@@ -923,7 +923,7 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
gpio_request(GPIO_PTE6, NULL);
gpio_request(GPIO_PTU1, NULL);
......@@ -935,7 +935,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTA2, 0);
/* I/O buffer drive ability is high */
ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
__raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
......@@ -1067,7 +1067,7 @@ static int __init arch_setup(void)
gpio_direction_output(GPIO_PTB7, 0);
/* I/O buffer drive ability is high for SDHI1 */
ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
#else
/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
......
......@@ -64,7 +64,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) {
if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) {
printk(KERN_INFO "Using r7780mp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;
......
......@@ -57,7 +57,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if (ctrl_inw(0xa5000600)) {
if (__raw_readw(0xa5000600)) {
printk(KERN_INFO "Using r7780rp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;
......
......@@ -66,20 +66,20 @@ static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
return NULL;
printk(KERN_INFO "Using r7785rp interrupt controller.\n");
ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
__raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
/* Setup the FPGA IRL */
ctrl_outw(0x0000, PA_IRLPRA); /* FPGA IRLA */
ctrl_outw(0xe598, PA_IRLPRB); /* FPGA IRLB */
ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */
ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */
ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */
ctrl_outw(0xdcba, PA_IRLPRF); /* FPGA IRLF */
__raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
__raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
__raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
__raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
__raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
__raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
register_intc_controller(&intc_desc);
return irl2irq;
......
......@@ -24,7 +24,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
unsigned int l, mask;
int ret = 0;
l = ctrl_inw(PA_DBSW);
l = __raw_readw(PA_DBSW);
/* Nothing to do if there's no state change */
if (psw->state) {
......@@ -45,7 +45,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
out:
/* Clear the switch IRQs */
l |= (0x7 << 12);
ctrl_outw(l, PA_DBSW);
__raw_writew(l, PA_DBSW);
return IRQ_RETVAL(ret);
}
......
......@@ -311,13 +311,13 @@ device_initcall(r7780rp_devices_setup);
*/
static int ivdr_clk_enable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
__raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
return 0;
}
static void ivdr_clk_disable(struct clk *clk)
{
ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
__raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
}
static struct clk_ops ivdr_clk_ops = {
......@@ -337,7 +337,7 @@ static struct clk *r7780rp_clocks[] = {
static void r7780rp_power_off(void)
{
if (mach_is_r7780mp() || mach_is_r7785rp())
ctrl_outw(0x0001, PA_POFF);
__raw_writew(0x0001, PA_POFF);
}
/*
......@@ -345,7 +345,7 @@ static void r7780rp_power_off(void)
*/
static void __init highlander_setup(char **cmdline_p)
{
u16 ver = ctrl_inw(PA_VERREG);
u16 ver = __raw_readw(PA_VERREG);
int i;
printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
......@@ -370,12 +370,12 @@ static void __init highlander_setup(char **cmdline_p)
clk_enable(clk);
}
ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
__raw_writew(0x0000, PA_OBLED); /* Clear LED. */
if (mach_is_r7780rp())
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
__raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
__raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
pm_power_off = r7780rp_power_off;
}
......
......@@ -53,7 +53,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info)
info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
APM_AC_ONLINE : APM_AC_OFFLINE;
pgdr = ctrl_inb(PGDR);
pgdr = __raw_readb(PGDR);
if (pgdr & PGDR_MAIN_BATTERY_OUT) {
info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
info->battery_flag = 0x80;
......
......@@ -53,17 +53,17 @@ static void pm_enter(void)
sh_wdt_write_cnt(0);
/* disable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr = __raw_readw(FRQCR);
frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
/* enable standby */
stbcr = ctrl_inb(STBCR);
ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
stbcr = __raw_readb(STBCR);
__raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
/* set self-refresh */
mcr = ctrl_inw(MCR);
ctrl_outw(mcr & ~MCR_RFSH, MCR);
mcr = __raw_readw(MCR);
__raw_writew(mcr & ~MCR_RFSH, MCR);
/* set interrupt handler */
asm volatile("stc vbr, %0" : "=r" (vbr_old));
......@@ -73,8 +73,8 @@ static void pm_enter(void)
&wakeup_start, &wakeup_end - &wakeup_start);
asm volatile("ldc %0, vbr" : : "r" (vbr_new));
ctrl_outw(0, RTCNT);
ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR);
__raw_writew(0, RTCNT);
__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
cpu_sleep();
......@@ -83,14 +83,14 @@ static void pm_enter(void)
free_page(vbr_new);
/* enable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr = __raw_readw(FRQCR);
frqcr |= FRQCR_PSTBY;
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
udelay(50);
frqcr |= FRQCR_PLLEN;
ctrl_outw(frqcr, FRQCR);
__raw_writew(frqcr, FRQCR);
ctrl_outb(stbcr, STBCR);
__raw_writeb(stbcr, STBCR);
clear_bl_bit();
}
......@@ -115,21 +115,21 @@ static int hp6x0_pm_enter(suspend_state_t state)
outw(hd64461_stbcr, HD64461_STBCR);
#endif
ctrl_outb(0x1f, DACR);
__raw_writeb(0x1f, DACR);
stbcr = ctrl_inb(STBCR);
ctrl_outb(0x01, STBCR);
stbcr = __raw_readb(STBCR);
__raw_writeb(0x01, STBCR);
stbcr2 = ctrl_inb(STBCR2);
ctrl_outb(0x7f , STBCR2);
stbcr2 = __raw_readb(STBCR2);
__raw_writeb(0x7f , STBCR2);
outw(0xf07f, HD64461_SCPUCR);
pm_enter();
outw(0, HD64461_SCPUCR);
ctrl_outb(stbcr, STBCR);
ctrl_outb(stbcr2, STBCR2);
__raw_writeb(stbcr, STBCR);
__raw_writeb(stbcr2, STBCR2);
#ifdef CONFIG_HD64461_ENABLER
hd64461_stbcr = inw(HD64461_STBCR);
......
......@@ -149,19 +149,19 @@ static void __init hp6xx_setup(char **cmdline_p)
sh_dac_output(0, DAC_SPEAKER_VOLUME);
sh_dac_disable(DAC_SPEAKER_VOLUME);
v8 = ctrl_inb(DACR);
v8 = __raw_readb(DACR);