Commit 9bbcbad4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'sound-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound fixes from Takashi Iwai:
 "Most of commits found here are for ASoC device specific fixes,
  arizona, cs4271, wm5102, wm2200, etc, in addition to a couple of
  memory leak fixes in ASoC core.

  Other than that, regression fixes in HD-audio and USB-audio, and a fix
  for new Realtek codecs."

* tag 'sound-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (30 commits)
  ALSA: usb-audio: Fix NULL dereference by access to non-existing substream
  ALSA: hda - Add support of new codec ALC284
  ALSA: usb-audio: Make ebox44_table static
  ALSA: hdspm - Fix wordclock status on AES32
  Revert "ALSA: hda - Shut up pins at power-saving mode with Conexnat codecs"
  ALSA: hda - Disable runtime D3 for Intel CPT & co
  ALSA: pxa27x: fix ac97 warm reset
  ALSA: pxa27x: fix ac97 cold reset
  ASoC: wm_adsp: Ensure that block writes are from DMA aligned addresses
  ASoC: wm2000: Fix sense of speech clarity enable
  ASoC: wm5100: Remove DSP B and left justified formats
  ASoC: arizona: Remove DSP B and left justified AIF modes
  ASoC: wm2200: Remove DSP B and left justified AIF modes
  ASoC: wm5102: Improve speaker enable performance
  ASoC: core: fix the memory leak in case of remove_aux_dev()
  ASoC: core: fix the memory leak in case of device_add() failure
  ASoC: cs42l52: Catch no-match case in cs42l52_get_clk
  ASoC: lm49453: Update lm49453_reg_defs values as per LM49453 HW revision-B
  ASoC: lm49453: Fix adc, mic and sidetone volume ranges
  ASoC: arizona: Correct FLL source definitions
  ...
parents b87fc3e6 31be5425
......@@ -463,6 +463,9 @@
GPIO76_LCD_PCLK, \
GPIO77_LCD_BIAS
/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */
#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT)
#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT)
extern int keypad_set_wake(unsigned int on);
#endif /* __ASM_ARCH_MFP_PXA27X_H */
......@@ -47,9 +47,9 @@ void pxa27x_clear_otgph(void)
EXPORT_SYMBOL(pxa27x_clear_otgph);
static unsigned long ac97_reset_config[] = {
GPIO113_GPIO,
GPIO113_AC97_nRESET_GPIO_HIGH,
GPIO113_AC97_nRESET,
GPIO95_GPIO,
GPIO95_AC97_nRESET_GPIO_HIGH,
GPIO95_AC97_nRESET,
};
......
......@@ -19,7 +19,7 @@
struct cs4271_platform_data {
int gpio_nreset; /* GPIO driving Reset pin, if any */
int amutec_eq_bmutec:1; /* flag to enable AMUTEC=BMUTEC */
bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
};
#endif /* __CS4271_H */
......@@ -58,8 +58,9 @@
.info = snd_soc_info_volsw_range, .get = snd_soc_get_volsw_range, \
.put = snd_soc_put_volsw_range, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = xshift, .min = xmin,\
.max = xmax, .platform_max = xmax, .invert = xinvert} }
{.reg = xreg, .rreg = xreg, .shift = xshift, \
.rshift = xshift, .min = xmin, .max = xmax, \
.platform_max = xmax, .invert = xinvert} }
#define SOC_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
......@@ -88,8 +89,9 @@
.info = snd_soc_info_volsw_range, \
.get = snd_soc_get_volsw_range, .put = snd_soc_put_volsw_range, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = xshift, .min = xmin,\
.max = xmax, .platform_max = xmax, .invert = xinvert} }
{.reg = xreg, .rreg = xreg, .shift = xshift, \
.rshift = xshift, .min = xmin, .max = xmax, \
.platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE(xname, reg, shift_left, shift_right, max, invert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
.info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \
......
......@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>
......@@ -148,6 +149,8 @@ static inline void pxa_ac97_warm_pxa27x(void)
static inline void pxa_ac97_cold_pxa27x(void)
{
unsigned int timeout;
GCR &= GCR_COLD_RST; /* clear everything but nCRST */
GCR &= ~GCR_COLD_RST; /* then assert nCRST */
......@@ -157,8 +160,10 @@ static inline void pxa_ac97_cold_pxa27x(void)
clk_enable(ac97conf_clk);
udelay(5);
clk_disable(ac97conf_clk);
GCR = GCR_COLD_RST;
udelay(50);
GCR = GCR_COLD_RST | GCR_WARM_RST;
timeout = 100; /* wait for the codec-ready bit to be set */
while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
mdelay(1);
}
#endif
......@@ -340,8 +345,21 @@ int pxa2xx_ac97_hw_probe(struct platform_device *dev)
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 as AC97 Reset on Bulverde */
/*
* This gpio is needed for a work-around to a bug in the ac97
* controller during warm reset. The direction and level is set
* here so that it is an output driven high when switching from
* AC97_nRESET alt function to generic gpio.
*/
ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
"pxa27x ac97 reset");
if (ret < 0) {
pr_err("%s: gpio_request_one() failed: %d\n",
__func__, ret);
goto err_conf;
}
pxa27x_assert_ac97reset(reset_gpio, 0);
ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
if (IS_ERR(ac97conf_clk)) {
ret = PTR_ERR(ac97conf_clk);
......@@ -384,6 +402,8 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
if (cpu_is_pxa27x())
gpio_free(reset_gpio);
GCR |= GCR_ACLINK_OFF;
free_irq(IRQ_AC97, NULL);
if (ac97conf_clk) {
......
......@@ -573,9 +573,12 @@ enum {
#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
/* quirks for Intel PCH */
#define AZX_DCAPS_INTEL_PCH \
#define AZX_DCAPS_INTEL_PCH_NOPM \
(AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
AZX_DCAPS_COUNT_LPIB_DELAY)
#define AZX_DCAPS_INTEL_PCH \
(AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
......@@ -3586,13 +3589,13 @@ static void azx_remove(struct pci_dev *pci)
static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
/* CPT */
{ PCI_DEVICE(0x8086, 0x1c20),
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
/* PBG */
{ PCI_DEVICE(0x8086, 0x1d20),
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
/* Panther Point */
{ PCI_DEVICE(0x8086, 0x1e20),
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
/* Lynx Point */
{ PCI_DEVICE(0x8086, 0x8c20),
.driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
......
......@@ -558,24 +558,12 @@ static int conexant_build_controls(struct hda_codec *codec)
return 0;
}
#ifdef CONFIG_PM
static int conexant_suspend(struct hda_codec *codec)
{
snd_hda_shutup_pins(codec);
return 0;
}
#endif
static const struct hda_codec_ops conexant_patch_ops = {
.build_controls = conexant_build_controls,
.build_pcms = conexant_build_pcms,
.init = conexant_init,
.free = conexant_free,
.set_power_state = conexant_set_power,
#ifdef CONFIG_PM
.suspend = conexant_suspend,
#endif
.reboot_notify = snd_hda_shutup_pins,
};
#ifdef CONFIG_SND_HDA_INPUT_BEEP
......@@ -4405,10 +4393,6 @@ static const struct hda_codec_ops cx_auto_patch_ops = {
.init = cx_auto_init,
.free = conexant_free,
.unsol_event = snd_hda_jack_unsol_event,
#ifdef CONFIG_PM
.suspend = conexant_suspend,
#endif
.reboot_notify = snd_hda_shutup_pins,
};
/*
......
......@@ -5817,6 +5817,9 @@ enum {
ALC269_TYPE_ALC269VB,
ALC269_TYPE_ALC269VC,
ALC269_TYPE_ALC269VD,
ALC269_TYPE_ALC280,
ALC269_TYPE_ALC282,
ALC269_TYPE_ALC284,
};
/*
......@@ -5833,10 +5836,13 @@ static int alc269_parse_auto_config(struct hda_codec *codec)
switch (spec->codec_variant) {
case ALC269_TYPE_ALC269VA:
case ALC269_TYPE_ALC269VC:
case ALC269_TYPE_ALC280:
case ALC269_TYPE_ALC284:
ssids = alc269va_ssids;
break;
case ALC269_TYPE_ALC269VB:
case ALC269_TYPE_ALC269VD:
case ALC269_TYPE_ALC282:
ssids = alc269_ssids;
break;
default:
......@@ -6400,7 +6406,8 @@ static int patch_alc269(struct hda_codec *codec)
alc_auto_parse_customize_define(codec);
if (codec->vendor_id == 0x10ec0269) {
switch (codec->vendor_id) {
case 0x10ec0269:
spec->codec_variant = ALC269_TYPE_ALC269VA;
switch (alc_get_coef0(codec) & 0x00f0) {
case 0x0010:
......@@ -6425,6 +6432,20 @@ static int patch_alc269(struct hda_codec *codec)
goto error;
spec->init_hook = alc269_fill_coef;
alc269_fill_coef(codec);
break;
case 0x10ec0280:
case 0x10ec0290:
spec->codec_variant = ALC269_TYPE_ALC280;
break;
case 0x10ec0282:
case 0x10ec0283:
spec->codec_variant = ALC269_TYPE_ALC282;
break;
case 0x10ec0284:
case 0x10ec0292:
spec->codec_variant = ALC269_TYPE_ALC284;
break;
}
/* automatic parse from the BIOS config */
......@@ -7129,6 +7150,7 @@ static const struct hda_codec_preset snd_hda_preset_realtek[] = {
{ .id = 0x10ec0280, .name = "ALC280", .patch = patch_alc269 },
{ .id = 0x10ec0282, .name = "ALC282", .patch = patch_alc269 },
{ .id = 0x10ec0283, .name = "ALC283", .patch = patch_alc269 },
{ .id = 0x10ec0284, .name = "ALC284", .patch = patch_alc269 },
{ .id = 0x10ec0290, .name = "ALC290", .patch = patch_alc269 },
{ .id = 0x10ec0292, .name = "ALC292", .patch = patch_alc269 },
{ .id = 0x10ec0861, .rev = 0x100340, .name = "ALC660",
......
......@@ -441,6 +441,7 @@ MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
*/
/* status */
#define HDSPM_AES32_wcLock 0x0200000
#define HDSPM_AES32_wcSync 0x0100000
#define HDSPM_AES32_wcFreq_bit 22
/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
HDSPM_bit2freq */
......@@ -3467,10 +3468,12 @@ static int hdspm_wc_sync_check(struct hdspm *hdspm)
switch (hdspm->io_type) {
case AES32:
status = hdspm_read(hdspm, HDSPM_statusRegister);
if (status & HDSPM_wcSync)
return 2;
else if (status & HDSPM_wcLock)
return 1;
if (status & HDSPM_AES32_wcLock) {
if (status & HDSPM_AES32_wcSync)
return 2;
else
return 1;
}
return 0;
break;
......@@ -4658,6 +4661,7 @@ snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
unsigned int status;
unsigned int status2;
unsigned int timecode;
unsigned int wcLock, wcSync;
int pref_syncref;
char *autosync_ref;
int x;
......@@ -4751,8 +4755,11 @@ snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
snd_iprintf(buffer, "--- Status:\n");
wcLock = status & HDSPM_AES32_wcLock;
wcSync = wcLock && (status & HDSPM_AES32_wcSync);
snd_iprintf(buffer, "Word: %s Frequency: %d\n",
(status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
(wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
for (x = 0; x < 8; x++) {
......
......@@ -446,15 +446,9 @@ static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_DSP_A:
mode = 0;
break;
case SND_SOC_DAIFMT_DSP_B:
mode = 1;
break;
case SND_SOC_DAIFMT_I2S:
mode = 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode = 3;
break;
default:
arizona_aif_err(dai, "Unsupported DAI format %d\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
......@@ -714,7 +708,8 @@ static int arizona_hw_params(struct snd_pcm_substream *substream,
snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK, 8);
ARIZONA_AIF1_RATE_MASK,
8 << ARIZONA_AIF1_RATE_SHIFT);
break;
default:
arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
......
......@@ -34,15 +34,15 @@
#define ARIZONA_FLL_SRC_MCLK1 0
#define ARIZONA_FLL_SRC_MCLK2 1
#define ARIZONA_FLL_SRC_SLIMCLK 2
#define ARIZONA_FLL_SRC_FLL1 3
#define ARIZONA_FLL_SRC_FLL2 4
#define ARIZONA_FLL_SRC_AIF1BCLK 5
#define ARIZONA_FLL_SRC_AIF2BCLK 6
#define ARIZONA_FLL_SRC_AIF3BCLK 7
#define ARIZONA_FLL_SRC_AIF1LRCLK 8
#define ARIZONA_FLL_SRC_AIF2LRCLK 9
#define ARIZONA_FLL_SRC_AIF3LRCLK 10
#define ARIZONA_FLL_SRC_SLIMCLK 3
#define ARIZONA_FLL_SRC_FLL1 4
#define ARIZONA_FLL_SRC_FLL2 5
#define ARIZONA_FLL_SRC_AIF1BCLK 8
#define ARIZONA_FLL_SRC_AIF2BCLK 9
#define ARIZONA_FLL_SRC_AIF3BCLK 10
#define ARIZONA_FLL_SRC_AIF1LRCLK 12
#define ARIZONA_FLL_SRC_AIF2LRCLK 13
#define ARIZONA_FLL_SRC_AIF3LRCLK 14
#define ARIZONA_MIXER_VOL_MASK 0x00FE
#define ARIZONA_MIXER_VOL_SHIFT 1
......
......@@ -474,16 +474,16 @@ static int cs4271_probe(struct snd_soc_codec *codec)
struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
int ret;
int gpio_nreset = -EINVAL;
int amutec_eq_bmutec = 0;
bool amutec_eq_bmutec = false;
#ifdef CONFIG_OF
if (of_match_device(cs4271_dt_ids, codec->dev)) {
gpio_nreset = of_get_named_gpio(codec->dev->of_node,
"reset-gpio", 0);
if (!of_get_property(codec->dev->of_node,
if (of_get_property(codec->dev->of_node,
"cirrus,amutec-eq-bmutec", NULL))
amutec_eq_bmutec = 1;
amutec_eq_bmutec = true;
}
#endif
......
......@@ -737,7 +737,7 @@ static const struct cs42l52_clk_para clk_map_table[] = {
static int cs42l52_get_clk(int mclk, int rate)
{
int i, ret = 0;
int i, ret = -EINVAL;
u_int mclk1, mclk2 = 0;
for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
......@@ -749,8 +749,6 @@ static int cs42l52_get_clk(int mclk, int rate)
}
}
}
if (ret > ARRAY_SIZE(clk_map_table))
return -EINVAL;
return ret;
}
......
......@@ -111,9 +111,9 @@ static struct reg_default lm49453_reg_defs[] = {
{ 101, 0x00 },
{ 102, 0x00 },
{ 103, 0x01 },
{ 105, 0x01 },
{ 106, 0x00 },
{ 107, 0x01 },
{ 104, 0x01 },
{ 105, 0x00 },
{ 106, 0x01 },
{ 107, 0x00 },
{ 108, 0x00 },
{ 109, 0x00 },
......@@ -163,56 +163,25 @@ static struct reg_default lm49453_reg_defs[] = {
{ 184, 0x00 },
{ 185, 0x00 },
{ 186, 0x00 },
{ 189, 0x00 },
{ 187, 0x00 },
{ 188, 0x00 },
{ 194, 0x00 },
{ 195, 0x00 },
{ 196, 0x00 },
{ 197, 0x00 },
{ 200, 0x00 },
{ 201, 0x00 },
{ 202, 0x00 },
{ 203, 0x00 },
{ 204, 0x00 },
{ 205, 0x00 },
{ 208, 0x00 },
{ 189, 0x00 },
{ 208, 0x06 },
{ 209, 0x00 },
{ 210, 0x00 },
{ 211, 0x00 },
{ 213, 0x00 },
{ 214, 0x00 },
{ 215, 0x00 },
{ 216, 0x00 },
{ 217, 0x00 },
{ 218, 0x00 },
{ 219, 0x00 },
{ 210, 0x08 },
{ 211, 0x54 },
{ 212, 0x14 },
{ 213, 0x0d },
{ 214, 0x0d },
{ 215, 0x14 },
{ 216, 0x60 },
{ 221, 0x00 },
{ 222, 0x00 },
{ 223, 0x00 },
{ 224, 0x00 },
{ 225, 0x00 },
{ 226, 0x00 },
{ 227, 0x00 },
{ 228, 0x00 },
{ 229, 0x00 },
{ 230, 0x13 },
{ 231, 0x00 },
{ 232, 0x80 },
{ 233, 0x0C },
{ 234, 0xDD },
{ 235, 0x00 },
{ 236, 0x04 },
{ 237, 0x00 },
{ 238, 0x00 },
{ 239, 0x00 },
{ 240, 0x00 },
{ 241, 0x00 },
{ 242, 0x00 },
{ 243, 0x00 },
{ 244, 0x00 },
{ 245, 0x00 },
{ 248, 0x00 },
{ 249, 0x00 },
{ 254, 0x00 },
{ 250, 0x00 },
{ 255, 0x00 },
};
......@@ -525,36 +494,41 @@ SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
};
/* TLV Declarations */
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7650, 150, 1);
static const DECLARE_TLV_DB_SCALE(port_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
/* Sidetone supports mono only */
SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
0, 0x3F, 0, digital_tlv),
0, 0x3F, 0, stn_tlv),
};
static const struct snd_kcontrol_new lm49453_snd_controls[] = {
/* mic1 and mic2 supports mono only */
SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_ADC_LEVELL_REG, 0, 6,
0, digital_tlv),
SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_ADC_LEVELR_REG, 0, 6,
0, digital_tlv),
SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
0, adc_dac_tlv),
SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
LM49453_P0_DMIC1_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
LM49453_P0_DMIC2_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
......@@ -569,16 +543,16 @@ static const struct snd_kcontrol_new lm49453_snd_controls[] = {
2, 1, 0),
SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
LM49453_P0_DAC_HP_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
LM49453_P0_DAC_LO_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
LM49453_P0_DAC_LS_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
LM49453_P0_DAC_HA_LEVELR_REG, 0, 6, 0, digital_tlv),
LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
0, 6, 0, digital_tlv),
0, 63, 0, adc_dac_tlv),
SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
0, 3, 0, port_tlv),
......@@ -1218,7 +1192,7 @@ static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
}
snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(1)|BIT(5),
LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
(aif_val | mode | clk_phase));
snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
......
......@@ -401,7 +401,7 @@ static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
5, 1, 0),
SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
0, 4, 0, mic_gain_tlv),
0, 3, 0, mic_gain_tlv),
};
/* mute the codec used by alsa core */
......@@ -1344,7 +1344,7 @@ static int sgtl5000_probe(struct snd_soc_codec *codec)
SGTL5000_HP_ZCD_EN |
SGTL5000_ADC_ZCD_EN);
snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
/*
* disable DAP
......
......@@ -74,9 +74,10 @@
SNDRV_PCM_FMTBIT_S32_LE)
#define S2PC_VALUE 0x98
#define CLOCK_OUT 0x60
#define LEFT_J_DATA_FORMAT 0x10
#define I2S_DATA_FORMAT 0x12
#define RIGHT_J_DATA_FORMAT 0x14
#define DATA_FORMAT_MSK 0x0E
#define LEFT_J_DATA_FORMAT 0x00
#define I2S_DATA_FORMAT 0x02
#define RIGHT_J_DATA_FORMAT 0x04
#define CODEC_MUTE_VAL 0x80
#define POWER_CNTLMSAK 0x40
......@@ -289,7 +290,7 @@ static int sta529_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
return -EINVAL;
}
snd_soc_update_bits(codec, STA529_S2PCFG0, 0x0D, mode);
snd_soc_update_bits(codec, STA529_S2PCFG0, DATA_FORMAT_MSK, mode);
return 0;
}
......
......@@ -209,9 +209,9 @@ static int wm2000_power_up(struct i2c_client *i2c, int analogue)
ret = wm2000_read(i2c, WM2000_REG_SPEECH_CLARITY);
if (wm2000->speech_clarity)
ret &= ~WM2000_SPEECH_CLARITY;
else
ret |= WM2000_SPEECH_CLARITY;
else
ret &= ~WM2000_SPEECH_CLARITY;
wm2000_write(i2c, WM2000_REG_SPEECH_CLARITY, ret);
wm2000_write(i2c, WM2000_REG_SYS_START0, 0x33);
......
......@@ -1566,15 +1566,9 @@ static int wm2200_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_DSP_A:
fmt_val = 0;
break;
case SND_SOC_DAIFMT_DSP_B:
fmt_val = 1;