Commit 9858a38e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
  sh: include Migo-R TS driver in Migo-R defconfig
  sh: correct definitions to access stack pointers
  sh: Tidy up SH-4A unaligned load support.
  dma: shdma: NMI support.
  sh: mach-sdk7786: Handle baseboard NMI source selection.
  sh: mach-rsk: Add polled GPIO buttons support for RSK+7203.
  sh: Break out cpuinfo_op procfs bits.
  sh: Enable optional gpiolib for all CPUs with pinmux tables.
  sh: migrate SH_CLK_MD to mode pin API.
  sh: machvec IO death.
parents abb35945 f862f904
......@@ -162,7 +162,8 @@ config ARCH_HAS_CPU_IDLE_WAIT
def_bool y
config NO_IOPORT
bool
def_bool !PCI
depends on !SH_CAYMAN && !SH_SH4202_MICRODEV
config IO_TRAPPED
bool
......@@ -275,6 +276,7 @@ config CPU_SUBTYPE_SH7203
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
select ARCH_WANT_OPTIONAL_GPIOLIB
config CPU_SUBTYPE_SH7206
bool "Support SH7206 processor"
......@@ -346,6 +348,7 @@ config CPU_SUBTYPE_SH7720
select CPU_SH3
select CPU_HAS_DSP
select SYS_SUPPORTS_CMT
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Select SH7720 if you have a SH3-DSP SH7720 CPU.
......@@ -408,6 +411,7 @@ config CPU_SUBTYPE_SH7723
select ARCH_SHMOBILE
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_CMT
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Select SH7723 if you have an SH-MobileR2 CPU.
......@@ -418,6 +422,7 @@ config CPU_SUBTYPE_SH7724
select ARCH_SHMOBILE
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_CMT
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Select SH7724 if you have an SH-MobileR2R CPU.
......@@ -425,6 +430,7 @@ config CPU_SUBTYPE_SH7757
bool "Support SH7757 processor"
select CPU_SH4A
select CPU_SHX2
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Select SH7757 if you have a SH4A SH7757 CPU.
......@@ -448,6 +454,7 @@ config CPU_SUBTYPE_SH7785
select CPU_SHX2
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
select ARCH_WANT_OPTIONAL_GPIOLIB
config CPU_SUBTYPE_SH7786
bool "Support SH7786 processor"
......@@ -455,6 +462,7 @@ config CPU_SUBTYPE_SH7786
select CPU_SHX3
select CPU_HAS_PTEAEX
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select ARCH_WANT_OPTIONAL_GPIOLIB
config CPU_SUBTYPE_SHX3
bool "Support SH-X3 processor"
......@@ -479,6 +487,7 @@ config CPU_SUBTYPE_SH7722
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_CMT
select ARCH_WANT_OPTIONAL_GPIOLIB
config CPU_SUBTYPE_SH7366
bool "Support SH7366 processor"
......@@ -568,15 +577,6 @@ config SH_CLK_CPG_LEGACY
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SHX3 && !CPU_SUBTYPE_SH7757
config SH_CLK_MD
int "CPU Mode Pin Setting"
depends on CPU_SH2
default 6 if CPU_SUBTYPE_SH7206
default 5 if CPU_SUBTYPE_SH7619
default 0
help
MD2 - MD0 pin setting.
source "kernel/time/Kconfig"
endmenu
......
......@@ -29,8 +29,6 @@ unsigned short secureedge5410_ioport;
*/
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
{
ctrl_delay(); /* dummy read */
printk("SnapGear: erase switch interrupt!\n");
return IRQ_HANDLED;
......
/*
* Renesas Technology Europe RSK+ 7203 Support.
*
* Copyright (C) 2008 Paul Mundt
* Copyright (C) 2008 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
......@@ -12,7 +12,9 @@
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/smsc911x.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <asm/machvec.h>
#include <asm/io.h>
......@@ -84,9 +86,42 @@ static struct platform_device led_device = {
},
};
static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
{
.code = BTN_0,
.gpio = GPIO_PB0,
.active_low = 1,
.desc = "SW1",
}, {
.code = BTN_1,
.gpio = GPIO_PB1,
.active_low = 1,
.desc = "SW2",
}, {
.code = BTN_2,
.gpio = GPIO_PB2,
.active_low = 1,
.desc = "SW3",
},
};
static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
.buttons = rsk7203_gpio_keys_table,
.nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table),
.poll_interval = 50, /* default to 50ms */
};
static struct platform_device keys_device = {
.name = "gpio-keys-polled",
.dev = {
.platform_data = &rsk7203_gpio_keys_info,
},
};
static struct platform_device *rsk7203_devices[] __initdata = {
&smsc911x_device,
&led_device,
&keys_device,
};
static int __init rsk7203_devices_setup(void)
......
obj-y := fpga.o irq.o setup.o
obj-y := fpga.o irq.o nmi.o setup.o
obj-$(CONFIG_GENERIC_GPIO) += gpio.o
obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o
/*
* SDK7786 FPGA NMI Support.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <mach/fpga.h>
enum {
NMI_MODE_MANUAL,
NMI_MODE_AUX,
NMI_MODE_MASKED,
NMI_MODE_ANY,
NMI_MODE_UNKNOWN,
};
/*
* Default to the manual NMI switch.
*/
static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
static int __init nmi_mode_setup(char *str)
{
if (!str)
return 0;
if (strcmp(str, "manual") == 0)
nmi_mode = NMI_MODE_MANUAL;
else if (strcmp(str, "aux") == 0)
nmi_mode = NMI_MODE_AUX;
else if (strcmp(str, "masked") == 0)
nmi_mode = NMI_MODE_MASKED;
else if (strcmp(str, "any") == 0)
nmi_mode = NMI_MODE_ANY;
else {
nmi_mode = NMI_MODE_UNKNOWN;
pr_warning("Unknown NMI mode %s\n", str);
}
printk("Set NMI mode to %d\n", nmi_mode);
return 0;
}
early_param("nmi_mode", nmi_mode_setup);
void __init sdk7786_nmi_init(void)
{
unsigned int source, mask, tmp;
switch (nmi_mode) {
case NMI_MODE_MANUAL:
source = NMISR_MAN_NMI;
mask = NMIMR_MAN_NMIM;
break;
case NMI_MODE_AUX:
source = NMISR_AUX_NMI;
mask = NMIMR_AUX_NMIM;
break;
case NMI_MODE_ANY:
source = NMISR_MAN_NMI | NMISR_AUX_NMI;
mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
break;
case NMI_MODE_MASKED:
case NMI_MODE_UNKNOWN:
default:
source = mask = 0;
break;
}
/* Set the NMI source */
tmp = fpga_read_reg(NMISR);
tmp &= ~NMISR_MASK;
tmp |= source;
fpga_write_reg(tmp, NMISR);
/* And the IRQ masking */
fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
}
......@@ -237,6 +237,7 @@ static void __init sdk7786_setup(char **cmdline_p)
pr_info("Renesas Technology Europe SDK7786 support:\n");
sdk7786_fpga_init();
sdk7786_nmi_init();
pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
......
......@@ -79,6 +79,11 @@ static int __init se7206_devices_setup(void)
}
__initcall(se7206_devices_setup);
static int se7206_mode_pins(void)
{
return MODE_PIN1 | MODE_PIN2;
}
/*
* The Machine Vector
*/
......@@ -87,4 +92,5 @@ static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_nr_irqs = 256,
.mv_init_irq = init_se7206_IRQ,
.mv_mode_pins = se7206_mode_pins,
};
......@@ -11,6 +11,11 @@
#include <asm/io.h>
#include <asm/machvec.h>
static int se7619_mode_pins(void)
{
return MODE_PIN2 | MODE_PIN0;
}
/*
* The Machine Vector
*/
......@@ -18,4 +23,5 @@
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_nr_irqs = 108,
.mv_mode_pins = se7619_mode_pins,
};
......@@ -54,6 +54,8 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_SH_KEYSC=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_MIGOR=y
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_SERIAL_SH_SCI=y
......
......@@ -382,14 +382,13 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
struct pci_channel *chan = dev->sysdata;
if (unlikely(!chan->io_map_base)) {
chan->io_map_base = generic_io_base;
chan->io_map_base = sh_io_port_base;
if (pci_domains_supported)
panic("To avoid data corruption io_map_base MUST be "
"set with multiple PCI domains.");
}
return (void __iomem *)(chan->io_map_base + port);
}
......
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H
/*
* Convention:
* read{b,w,l,q}/write{b,w,l,q} are for PCI,
......@@ -15,12 +16,6 @@
* SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
* these have the same semantics as the __raw variants, and as such, all
* new code should be using the __raw versions.
*
* All ISA I/O routines are wrapped through the machine vector. If a
* board does not provide overrides, a generic set that are copied in
* from the default machine vector are used instead. These are largely
* for old compat code for I/O offseting to SuperIOs, all of which are
* better handled through the machvec ioport mapping routines these days.
*/
#include <linux/errno.h>
#include <asm/cache.h>
......@@ -31,39 +26,10 @@
#include <asm-generic/iomap.h>
#ifdef __KERNEL__
/*
* Depending on which platform we are running on, we need different
* I/O functions.
*/
#define __IO_PREFIX generic
#define __IO_PREFIX generic
#include <asm/io_generic.h>
#include <asm/io_trapped.h>
#ifdef CONFIG_HAS_IOPORT
#define inb(p) sh_mv.mv_inb((p))
#define inw(p) sh_mv.mv_inw((p))
#define inl(p) sh_mv.mv_inl((p))
#define outb(x,p) sh_mv.mv_outb((x),(p))
#define outw(x,p) sh_mv.mv_outw((x),(p))
#define outl(x,p) sh_mv.mv_outl((x),(p))
#define inb_p(p) sh_mv.mv_inb_p((p))
#define inw_p(p) sh_mv.mv_inw_p((p))
#define inl_p(p) sh_mv.mv_inl_p((p))
#define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
#define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
#define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
#define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
#define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
#define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
#endif
#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
......@@ -74,68 +40,39 @@
#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
#define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; })
#define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; })
#define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; })
#define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; })
#define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
#define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
#define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
#define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); })
/*
* Legacy SuperH on-chip I/O functions
*
* These are all deprecated, all new (and especially cross-platform) code
* should be using the __raw_xxx() routines directly.
*/
static inline u8 __deprecated ctrl_inb(unsigned long addr)
{
return __raw_readb(addr);
}
static inline u16 __deprecated ctrl_inw(unsigned long addr)
{
return __raw_readw(addr);
}
static inline u32 __deprecated ctrl_inl(unsigned long addr)
{
return __raw_readl(addr);
}
static inline u64 __deprecated ctrl_inq(unsigned long addr)
{
return __raw_readq(addr);
}
static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
{
__raw_writeb(v, addr);
}
static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
{
__raw_writew(v, addr);
}
static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
{
__raw_writel(v, addr);
}
static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
{
__raw_writeq(v, addr);
}
extern unsigned long generic_io_base;
static inline void ctrl_delay(void)
{
__raw_readw(generic_io_base);
}
#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
__raw_readw(c)); __v; })
#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
__raw_readl(c)); __v; })
#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64) \
__raw_readq(c)); __v; })
#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
cpu_to_le16(v),c))
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
cpu_to_le32(v),c))
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
cpu_to_le64(v),c))
#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
#define readsb(p,d,l) __raw_readsb(p,d,l)
#define readsw(p,d,l) __raw_readsw(p,d,l)
#define readsl(p,d,l) __raw_readsl(p,d,l)
#define writesb(p,d,l) __raw_writesb(p,d,l)
#define writesw(p,d,l) __raw_writesw(p,d,l)
#define writesl(p,d,l) __raw_writesl(p,d,l)
#define __BUILD_UNCACHED_IO(bwlq, type) \
static inline type read##bwlq##_uncached(unsigned long addr) \
......@@ -159,10 +96,11 @@ __BUILD_UNCACHED_IO(w, u16)
__BUILD_UNCACHED_IO(l, u32)
__BUILD_UNCACHED_IO(q, u64)
#define __BUILD_MEMORY_STRING(bwlq, type) \
#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
\
static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
const void *addr, unsigned int count) \
static inline void \
pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
unsigned int count) \
{ \
const volatile type *__addr = addr; \
\
......@@ -172,8 +110,8 @@ static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
} \
} \
\
static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
void *addr, unsigned int count) \
static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
void *addr, unsigned int count) \
{ \
volatile type *__addr = addr; \
\
......@@ -183,85 +121,166 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
} \
}
__BUILD_MEMORY_STRING(b, u8)
__BUILD_MEMORY_STRING(w, u16)
__BUILD_MEMORY_STRING(__raw_, b, u8)
__BUILD_MEMORY_STRING(__raw_, w, u16)
#ifdef CONFIG_SUPERH32
void __raw_writesl(void __iomem *addr, const void *data, int longlen);
void __raw_readsl(const void __iomem *addr, void *data, int longlen);
#else
__BUILD_MEMORY_STRING(l, u32)
__BUILD_MEMORY_STRING(__raw_, l, u32)
#endif
__BUILD_MEMORY_STRING(q, u64)
#define writesb __raw_writesb
#define writesw __raw_writesw
#define writesl __raw_writesl
#define readsb __raw_readsb
#define readsw __raw_readsw
#define readsl __raw_readsl
#define readb_relaxed(a) readb(a)
#define readw_relaxed(a) readw(a)
#define readl_relaxed(a) readl(a)
#define readq_relaxed(a) readq(a)
#ifndef CONFIG_GENERIC_IOMAP
/* Simple MMIO */
#define ioread8(a) __raw_readb(a)
#define ioread16(a) __raw_readw(a)
#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
#define ioread32(a) __raw_readl(a)
#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
#define iowrite8(v,a) __raw_writeb((v),(a))
#define iowrite16(v,a) __raw_writew((v),(a))
#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
#define iowrite32(v,a) __raw_writel((v),(a))
#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
#define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
#define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
#define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
__BUILD_MEMORY_STRING(__raw_, q, u64)
#ifdef CONFIG_HAS_IOPORT
/*
* Slowdown I/O port space accesses for antique hardware.
*/
#undef CONF_SLOWDOWN_IO
/*
* On SuperH I/O ports are memory mapped, so we access them using normal
* load/store instructions. sh_io_port_base is the virtual address to
* which all ports are being mapped.
*/
extern const unsigned long sh_io_port_base;
static inline void __set_io_port_base(unsigned long pbase)
{
*(unsigned long *)&sh_io_port_base = pbase;
barrier();
}
#ifdef CONFIG_GENERIC_IOMAP
#define __ioport_map ioport_map
#else
extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
#endif
#define mmio_insb(p,d,c) __raw_readsb(p,d,c)
#define mmio_insw(p,d,c) __raw_readsw(p,d,c)
#define mmio_insl(p,d,c) __raw_readsl(p,d,c)
#ifdef CONF_SLOWDOWN_IO
#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
#else
#define SLOW_DOWN_IO
#endif
#define mmio_outsb(p,s,c) __raw_writesb(p,s,c)
#define mmio_outsw(p,s,c) __raw_writesw(p,s,c)
#define mmio_outsl(p,s,c) __raw_writesl(p,s,c)
#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
\
static inline void pfx##out##bwlq##p(type val, unsigned long port) \
{ \
volatile type *__addr; \
\
__addr = __ioport_map(port, sizeof(type)); \
*__addr = val; \
slow; \
} \
\
static inline type pfx##in##bwlq##p(unsigned long port) \
{ \
volatile type *__addr; \
type __val; \
\
__addr = __ioport_map(port, sizeof(type)); \
__val = *__addr; \
slow; \
\
return __val; \
}
/* synco on SH-4A, otherwise a nop */
#define mmiowb() wmb()
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
#define IO_SPACE_LIMIT 0xffffffff
#define BUILDIO_IOPORT(bwlq, type) \
__BUILD_IOPORT_PFX(, bwlq, type)
#ifdef CONFIG_HAS_IOPORT
BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)