Commit 974b3358 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "People are back from the holiday breaks, and it shows.  Here are a
  bunch of fixes for a number of platforms:
   - A couple of small fixes for Nomadik
   - A larger set of changes for kirkwood/mvebu
     - uart driver selection, dt clocks, gpio-poweroff fixups, a few
       __init annotation fixes and some error handling improvement in
       their xor dma driver.
   - i.MX had a couple of minor fixes (and a critical one for flexcan2
     clock setup)
   - MXS has a small board fix and a framebuffer bugfix
   - A set of fixes for Samsung Exynos, fixing default bootargs and some
     Exynos5440 clock issues
   - A set of OMAP changes including PM fixes and a few sparse warning
     fixups

  All in all a bit more positive code delta than we'd ideally want to
  see here, mostly from the OMAP PM changes, but nothing overly crazy."

* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
  ARM: clps711x: Fix bad merge of clockevents setup
  ARM: highbank: save and restore L2 cache and GIC on suspend
  ARM: highbank: add a power request clear
  ARM: highbank: fix secondary boot and hotplug
  ARM: highbank: fix typos with hignbank in power request functions
  ARM: dts: fix highbank cpu mpidr values
  ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
  ARM: mx5: Fix MX53 flexcan2 clock
  ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
  pinctrl: mvebu: make pdma clock on dove mandatory
  ARM: Dove: Add pinctrl clock to DT
  dma: mv_xor: fix error handling for clocks
  dma: mv_xor: fix error handling of mv_xor_channel_add()
  arm: mvebu: Add missing ; for cpu node.
  arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
  arm: mvebu: Armada XP MV78230 has two cores, not one
  clk: mvebu: Remove inappropriate __init tagging
  ARM: Kirkwood: Use fixed-regulator instead of board gpio call
  ARM: Kirkwood: Fix missing sdio clock
  ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
  ...
parents ca5c8a4c 434fec16
......@@ -60,11 +60,6 @@ clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
clock-output-names =
...
"uart", /* 32 */
...
"end_of_list";
};
auart0: serial@8006c000 {
......
......@@ -146,10 +146,6 @@ clks: ccm@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
clock-output-names = ...
"uart_ipg",
"uart_serial",
...;
};
uart1: serial@43f90000 {
......
......@@ -83,11 +83,6 @@ clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
clock-output-names =
...
"uart", /* 45 */
...
"end_of_list";
};
auart0: serial@8006a000 {
......
......@@ -211,10 +211,6 @@ clks: ccm@020c4000 {
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
clock-output-names = ...
"uart_ipg",
"uart_serial",
...;
};
uart1: serial@02020000 {
......
GPIO line that should be set high/low to power off a device
Driver a GPIO line that can be used to turn the power off.
The driver supports both level triggered and edge triggered power off.
At driver load time, the driver will request the given gpio line and
install a pm_power_off handler. If the optional properties 'input' is
not found, the GPIO line will be driven in the inactive
state. Otherwise its configured as an input.
When the pm_power_off is called, the gpio is configured as an output,
and drive active, so triggering a level triggered power off
condition. This will also cause an inactive->active edge condition, so
triggering positive edge triggered power off. After a delay of 100ms,
the GPIO is set to inactive, thus causing an active->inactive edge,
triggering negative edge triggered power off. After another 100ms
delay the GPIO is driver active again. If the power is still on and
the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted.
Required properties:
- compatible : should be "gpio-poweroff".
......@@ -13,10 +28,9 @@ Optional properties:
property is not specified, the GPIO is initialized as an output in its
inactive state.
Examples:
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
gpios = <&gpio 4 0>;
};
......@@ -371,7 +371,6 @@ config ARCH_CNS3XXX
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select COMMON_CLK
......
......@@ -50,17 +50,19 @@
ranges;
serial@d0012000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0xd0012000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <4>;
status = "disabled";
};
serial@d0012100 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0xd0012100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <4>;
status = "disabled";
};
......
......@@ -34,7 +34,14 @@
reg = <0>;
clocks = <&cpuclk 0>;
};
}
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
};
soc {
pinctrl {
......
......@@ -85,5 +85,13 @@
#interrupts-cells = <2>;
interrupts = <24>;
};
ethernet@d0034000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
};
};
......@@ -100,5 +100,13 @@
#interrupts-cells = <2>;
interrupts = <24>;
};
ethernet@d0034000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
};
};
......@@ -42,17 +42,19 @@
soc {
serial@d0012200 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>;
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <4>;
status = "disabled";
};
serial@d0012300 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0xd0012300 0x100>;
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <4>;
status = "disabled";
};
......@@ -93,14 +95,6 @@
status = "disabled";
};
ethernet@d0034000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
xor@d0060900 {
compatible = "marvell,orion-xor";
reg = <0xd0060900 0x100
......
......@@ -117,6 +117,7 @@
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x10>;
clocks = <&gate_clk 22>;
};
spi0: spi@10600 {
......
......@@ -32,6 +32,7 @@
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <0>;
clocks = <&a9pll>;
clock-names = "cpu";
......@@ -39,6 +40,7 @@
cpu@1 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <1>;
clocks = <&a9pll>;
clock-names = "cpu";
......@@ -46,6 +48,7 @@
cpu@2 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <2>;
clocks = <&a9pll>;
clock-names = "cpu";
......@@ -53,6 +56,7 @@
cpu@3 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <3>;
clocks = <&a9pll>;
clock-names = "cpu";
......
......@@ -26,7 +26,7 @@
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
};
sdhci@12530000 {
......
......@@ -574,7 +574,7 @@
hdmi {
compatible = "samsung,exynos5-hdmi";
reg = <0x14530000 0x100000>;
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
};
......
......@@ -21,7 +21,7 @@
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
};
spi {
......
......@@ -30,33 +30,37 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu@900 {
compatible = "arm,cortex-a9";
reg = <0>;
device_type = "cpu";
reg = <0x900>;
next-level-cache = <&L2>;
clocks = <&a9pll>;
clock-names = "cpu";
};
cpu@1 {
cpu@901 {
compatible = "arm,cortex-a9";
reg = <1>;
device_type = "cpu";
reg = <0x901>;
next-level-cache = <&L2>;
clocks = <&a9pll>;
clock-names = "cpu";
};
cpu@2 {
cpu@902 {
compatible = "arm,cortex-a9";
reg = <2>;
device_type = "cpu";
reg = <0x902>;
next-level-cache = <&L2>;
clocks = <&a9pll>;
clock-names = "cpu";
};
cpu@3 {
cpu@903 {
compatible = "arm,cortex-a9";
reg = <3>;
device_type = "cpu";
reg = <0x903>;
next-level-cache = <&L2>;
clocks = <&a9pll>;
clock-names = "cpu";
......
......@@ -39,17 +39,17 @@
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
led_pin_gpio0_17: led_gpio0_17@0 {
led_pin_gpio2_1: led_gpio2_1@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
......@@ -110,7 +110,7 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio0_17>;
pinctrl-0 = <&led_pin_gpio2_1>;
user {
label = "green";
......
......@@ -14,7 +14,7 @@
/ {
model = "Buglabs i.MX31 Bug 1.x";
compatible = "fsl,imx31-bug", "fsl,imx31";
compatible = "buglabs,imx31-bug", "fsl,imx31";
memory {
reg = <0x80000000 0x8000000>; /* 128M */
......
......@@ -492,7 +492,7 @@
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks 158>, <&clks 157>;
clocks = <&clks 87>, <&clks 86>;
clock-names = "ipg", "per";
status = "disabled";
};
......
......@@ -39,6 +39,7 @@
#size-cells = <0>;
interrupts = <32>;
clock-frequency = <100000>;
clocks = <&gate_clk 7>;
status = "disabled";
};
};
......
......@@ -82,4 +82,21 @@
gpios = <&gpio1 16 1>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
sata0_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA0 Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 4 0>;
};
};
};
......@@ -144,6 +144,7 @@
compatible = "marvell,orion-ehci";
reg = <0x50000 0x1000>;
interrupts = <19>;
clocks = <&gate_clk 3>;
status = "okay";
};
......
......@@ -33,9 +33,7 @@ CONFIG_MVNETA=y
CONFIG_MARVELL_PHY=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_MV64XXX=y
CONFIG_SERIAL_8250_DW=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_USB_SUPPORT is not set
......
......@@ -74,6 +74,8 @@ config SOC_EXYNOS5440
depends on ARCH_EXYNOS5
select ARM_ARCH_TIMER
select AUTO_ZRELADDR
select PINCTRL
select PINCTRL_EXYNOS5440
help
Enable EXYNOS5440 SoC support
......
......@@ -424,11 +424,18 @@ static void __init exynos5_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
/* EXYNOS5440 can support only common clock framework */
if (soc_is_exynos5440())
return;
#ifdef CONFIG_SOC_EXYNOS5250
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
exynos5_register_clocks();
exynos5_setup_clocks();
#endif
}
#define COMBINER_ENABLE_SET 0x0
......
......@@ -135,7 +135,7 @@ static struct sys_timer highbank_timer = {
static void highbank_power_off(void)
{
hignbank_set_pwr_shutdown();
highbank_set_pwr_shutdown();
while (1)
cpu_do_idle();
......
......@@ -30,7 +30,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
{
flush_cache_all();
highbank_set_cpu_jump(cpu, secondary_startup);
highbank_set_cpu_jump(cpu, phys_to_virt(0));
highbank_set_core_pwr();
cpu_do_idle();
......
......@@ -32,6 +32,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
gic_raise_softirq(cpumask_of(cpu), 0);
return 0;
}
......@@ -61,19 +62,8 @@ static void __init highbank_smp_init_cpus(void)
static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
if (scu_base_addr)
scu_enable(scu_base_addr);
/*
* Write the address of secondary startup into the jump table
* The cores are in wfi and wait until they receive a soft interrupt
* and a non-zero value to jump to. Then the secondary CPU branches
* to this address.
*/
for (i = 1; i < max_cpus; i++)
highbank_set_cpu_jump(i, secondary_startup);
}
struct smp_operations highbank_smp_ops __initdata = {
......
......@@ -14,10 +14,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/cpu_pm.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/suspend.h>
#include <asm/cacheflush.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
......@@ -26,16 +28,31 @@
static int highbank_suspend_finish(unsigned long val)
{
outer_flush_all();
outer_disable();
highbank_set_pwr_suspend();
cpu_do_idle();
highbank_clear_pwr_request();
return 0;
}
static int highbank_pm_enter(suspend_state_t state)
{
hignbank_set_pwr_suspend();
cpu_pm_enter();
cpu_cluster_pm_enter();
highbank_set_cpu_jump(0, cpu_resume);
cpu_suspend(0, highbank_suspend_finish);
cpu_cluster_pm_exit();
cpu_pm_exit();
highbank_smc1(0x102, 0x1);
if (scu_base_addr)
scu_enable(scu_base_addr);
return 0;
}
......
......@@ -44,28 +44,43 @@ static inline void highbank_set_core_pwr(void)
writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
}
static inline void hignbank_set_pwr_suspend(void)
static inline void highbank_clear_core_pwr(void)
{
int cpu = cpu_logical_map(smp_processor_id());
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
else
writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
}
static inline void highbank_set_pwr_suspend(void)
{
writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void hignbank_set_pwr_shutdown(void)
static inline void highbank_set_pwr_shutdown(void)
{
writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void hignbank_set_pwr_soft_reset(void)
static inline void highbank_set_pwr_soft_reset(void)
{
writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void hignbank_set_pwr_hard_reset(void)
static inline void highbank_set_pwr_hard_reset(void)
{
writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_set_core_pwr();
}
static inline void highbank_clear_pwr_request(void)
{
writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
highbank_clear_core_pwr();
}
#endif
......@@ -22,9 +22,9 @@
void highbank_restart(char mode, const char *cmd)
{
if (mode == 'h')
hignbank_set_pwr_hard_reset();
highbank_set_pwr_hard_reset();
else
hignbank_set_pwr_soft_reset();
highbank_set_pwr_soft_reset();
while (1)
cpu_do_idle();
......
......@@ -67,6 +67,10 @@ static void __init kirkwood_legacy_clk_init(void)
orion_clkdev_add(NULL, "mv643xx_eth_port.1",
of_clk_get_from_provider(&clkspec));
clkspec.args[0] = CGC_BIT_SDIO;
orion_clkdev_add(NULL, "mvsdio",
of_clk_get_from_provider(&clkspec));
}
static void __init kirkwood_of_clk_init(void)
......
......@@ -64,8 +64,6 @@ static unsigned int topkick_mpp_config[] __initdata = {
0
};
#define TOPKICK_SATA0_PWR_ENABLE 36
void __init usi_topkick_init(void)
{
/*
......@@ -73,8 +71,6 @@ void __init usi_topkick_init(void)
*/
kirkwood_mpp_conf(topkick_mpp_config);
/* SATA0 power enable */
gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1);
kirkwood_ge00_init(&topkick_ge00_data);
kirkwood_sdio_init(&topkick_mvsdio_data);
......
......@@ -27,7 +27,6 @@
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <linux/platform_data/mtd-nomadik-nand.h>
#include <asm/hardware/vic.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
......
......@@ -22,49 +22,49 @@
#include <mach/hardware.h>
#define IRQ_VIC_START 1 /* first VIC interrupt is 1 */
#define IRQ_VIC_START 32 /* first VIC interrupt is 1 */
/*
* Interrupt numbers generic for all Nomadik Chip cuts
*/
#define IRQ_WATCHDOG 1
#define IRQ_SOFTINT 2
#define IRQ_CRYPTO 3
#define IRQ_OWM 4
#define IRQ_MTU0 5
#define IRQ_MTU1 6
#define IRQ_GPIO0 7
#define IRQ_GPIO1 8
#define IRQ_GPIO2 9
#define IRQ_GPIO3 10
#define IRQ_RTC_RTT 11
#define IRQ_SSP 12
#define IRQ_UART0 13
#define IRQ_DMA1 14
#define IRQ_CLCD_MDIF 15
#define IRQ_DMA0 16
#define IRQ_PWRFAIL 17
#define IRQ_UART1 18
#define IRQ_FIRDA 19
#define IRQ_MSP0 20
#define IRQ_I2C0 21
#define IRQ_I2C1 22
#define IRQ_SDMMC 23
#define IRQ_USBOTG 24
#define IRQ_SVA_IT0 25
#define IRQ_SVA_IT1 26
#define IRQ_SAA_IT0 27
#define IRQ_SAA_IT1 28
#define IRQ_UART2 29
#define IRQ_MSP2 30
#define IRQ_L2CC 49
#define IRQ_HPI 50
#define IRQ_SKE 51
#define IRQ_KP 52
#define IRQ_MEMST 55
#define IRQ_SGA_IT 59
#define IRQ_USBM 61
#define IRQ_MSP1 63
#define IRQ_WATCHDOG (IRQ_VIC_START+0)
#define IRQ_SOFTINT (IRQ_VIC_START+1)
#define IRQ_CRYPTO (IRQ_VIC_START+2)
#define IRQ_OWM (IRQ_VIC_START+3)
#define IRQ_MTU0 (IRQ_VIC_START+4)
#define IRQ_MTU1 (IRQ_VIC_START+5)
#define IRQ_GPIO0 (IRQ_VIC_START+6)
#define IRQ_GPIO1 (IRQ_VIC_START+7)
#define IRQ_GPIO2 (IRQ_VIC_START+8)
#define IRQ_GPIO3 (IRQ_VIC_START+9)
#define IRQ_RTC_RTT (IRQ_VIC_START+10)
#define IRQ_SSP (IRQ_VIC_START+11)
#define IRQ_UART0 (IRQ_VIC_START+12)
#define IRQ_DMA1 (IRQ_VIC_START+13)
#define IRQ_CLCD_MDIF (IRQ_VIC_START+14)
#define IRQ_DMA0 (IRQ_VIC_START+15)
#define IRQ_PWRFAIL (IRQ_VIC_START+16)
#define IRQ_UART1 (IRQ_VIC_START+17)
#define IRQ_FIRDA (IRQ_VIC_START+18)
#define IRQ_MSP0 (IRQ_VIC_START+19)
#define IRQ_I2C0 (IRQ_VIC_START+20)
#define IRQ_I2C1 (IRQ_VIC_START+21)
#define IRQ_SDMMC (IRQ_VIC_START+22)
#define IRQ_USBOTG (IRQ_VIC_START+23)
#define IRQ_SVA_IT0 (IRQ_VIC_START+24)
#define IRQ_SVA_IT1 (IRQ_VIC_START+25)
#define IRQ_SAA_IT0 (IRQ_VIC_START+26)
#define IRQ_SAA_IT1 (IRQ_VIC_START+27)
#define IRQ_UART2 (IRQ_VIC_START+28)
#define IRQ_MSP2 (IRQ_VIC_START+29)
#define IRQ_L2CC (IRQ_VIC_START+30)
#define IRQ_HPI (IRQ_VIC_START+31)
#define IRQ_SKE (IRQ_VIC_START+32)
#define IRQ_KP (IRQ_VIC_START+33)
#define IRQ_MEMST (IRQ_VIC_START+34)
#define IRQ_SGA_IT (IRQ_VIC_START+35)
#define IRQ_USBM (IRQ_VIC_START+36)
#define IRQ_MSP1 (IRQ_VIC_START+37)
#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64)