Commit 9581960a authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 8055/1: cacheflush: use -st dsb option for ensuring completion



dsb st can be used to ensure completion of pending cache maintenance
operations, so use it for the v7 cache maintenance operations.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent cd000cf6
...@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, ...@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
static inline void __flush_icache_all(void) static inline void __flush_icache_all(void)
{ {
__flush_icache_preferred(); __flush_icache_preferred();
dsb(); dsb(ishst);
} }
/* /*
......
...@@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1) ...@@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
bgt 2b bgt 2b
cmp r2, #0 cmp r2, #0
bgt 1b bgt 1b
dsb dsb st
isb isb
mov pc, lr mov pc, lr
ENDPROC(v7_invalidate_l1) ENDPROC(v7_invalidate_l1)
...@@ -166,7 +166,7 @@ skip: ...@@ -166,7 +166,7 @@ skip:
finished: finished:
mov r10, #0 @ swith back to cache level 0 mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
dsb dsb st
isb isb
mov pc, lr mov pc, lr
ENDPROC(v7_flush_dcache_all) ENDPROC(v7_flush_dcache_all)
...@@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area) ...@@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
add r0, r0, r2 add r0, r0, r2
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
dsb dsb st
mov pc, lr mov pc, lr
ENDPROC(v7_flush_kern_dcache_area) ENDPROC(v7_flush_kern_dcache_area)
...@@ -368,7 +368,7 @@ v7_dma_inv_range: ...@@ -368,7 +368,7 @@ v7_dma_inv_range:
add r0, r0, r2 add r0, r0, r2
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
dsb dsb st
mov pc, lr mov pc, lr
ENDPROC(v7_dma_inv_range) ENDPROC(v7_dma_inv_range)
...@@ -390,7 +390,7 @@ v7_dma_clean_range: ...@@ -390,7 +390,7 @@ v7_dma_clean_range:
add r0, r0, r2 add r0, r0, r2
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
dsb dsb st
mov pc, lr mov pc, lr
ENDPROC(v7_dma_clean_range) ENDPROC(v7_dma_clean_range)
...@@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range) ...@@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
add r0, r0, r2 add r0, r0, r2
cmp r0, r1 cmp r0, r1
blo 1b blo 1b
dsb dsb st
mov pc, lr mov pc, lr
ENDPROC(v7_dma_flush_range) ENDPROC(v7_dma_flush_range)
......
...@@ -1465,7 +1465,7 @@ void __init early_paging_init(const struct machine_desc *mdesc, ...@@ -1465,7 +1465,7 @@ void __init early_paging_init(const struct machine_desc *mdesc,
* just complicate the code. * just complicate the code.
*/ */
flush_cache_louis(); flush_cache_louis();
dsb(); dsb(ishst);
isb(); isb();
/* remap level 1 table */ /* remap level 1 table */
......
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