Commit 925ddb04 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle
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Mask and ack CPU interrupts upon initialization. Keep the state


of software interrupts when unmasking.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 38b18f72
...@@ -3,6 +3,8 @@ ...@@ -3,6 +3,8 @@
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* *
* Copyright (C) 2001 Ralf Baechle * Copyright (C) 2001 Ralf Baechle
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
* Author: Maciej W. Rozycki <macro@mips.com>
* *
* This file define the irq handler for MIPS CPU interrupts. * This file define the irq handler for MIPS CPU interrupts.
* *
...@@ -37,7 +39,6 @@ static int mips_cpu_irq_base; ...@@ -37,7 +39,6 @@ static int mips_cpu_irq_base;
static inline void unmask_mips_irq(unsigned int irq) static inline void unmask_mips_irq(unsigned int irq)
{ {
clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
set_c0_status(0x100 << (irq - mips_cpu_irq_base)); set_c0_status(0x100 << (irq - mips_cpu_irq_base));
} }
...@@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base) ...@@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base)
{ {
int i; int i;
/* Mask interrupts. */
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
for (i = irq_base; i < irq_base + 8; i++) { for (i = irq_base; i < irq_base + 8; i++) {
irq_desc[i].status = IRQ_DISABLED; irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL; irq_desc[i].action = NULL;
......
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