Commit 87aa1328 authored by James Hogan's avatar James Hogan
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metag: Header for core memory mapped registers



Add the header <asm/metag_mem.h> describing addresses, fields, and bits
of various core memory mapped registers in the low non-MMU region.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
parent af8a1049
/*
* asm/metag_mem.h
*
* Copyright (C) 2000-2007, 2012 Imagination Technologies.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*
* Various defines for Meta (memory-mapped) registers.
*/
#ifndef _ASM_METAG_MEM_H_
#define _ASM_METAG_MEM_H_
/*****************************************************************************
* META MEMORY MAP LINEAR ADDRESS VALUES
****************************************************************************/
/*
* COMMON MEMORY MAP
* -----------------
*/
#define LINSYSTEM_BASE 0x00200000
#define LINSYSTEM_LIMIT 0x07FFFFFF
/* Linear cache flush now implemented via DCACHE instruction. These defines
related to a special region that used to exist for achieving cache flushes.
*/
#define LINSYSLFLUSH_S 0
#define LINSYSRES0_BASE 0x00200000
#define LINSYSRES0_LIMIT 0x01FFFFFF
#define LINSYSCUSTOM_BASE 0x02000000
#define LINSYSCUSTOM_LIMIT 0x02FFFFFF
#define LINSYSEXPAND_BASE 0x03000000
#define LINSYSEXPAND_LIMIT 0x03FFFFFF
#define LINSYSEVENT_BASE 0x04000000
#define LINSYSEVENT_WR_ATOMIC_UNLOCK 0x04000000
#define LINSYSEVENT_WR_ATOMIC_LOCK 0x04000040
#define LINSYSEVENT_WR_CACHE_DISABLE 0x04000080
#define LINSYSEVENT_WR_CACHE_ENABLE 0x040000C0
#define LINSYSEVENT_WR_COMBINE_FLUSH 0x04000100
#define LINSYSEVENT_WR_FENCE 0x04000140
#define LINSYSEVENT_LIMIT 0x04000FFF
#define LINSYSCFLUSH_BASE 0x04400000
#define LINSYSCFLUSH_DCACHE_LINE 0x04400000
#define LINSYSCFLUSH_ICACHE_LINE 0x04500000
#define LINSYSCFLUSH_MMCU 0x04700000
#ifndef METAC_1_2
#define LINSYSCFLUSH_TxMMCU_BASE 0x04700020
#define LINSYSCFLUSH_TxMMCU_STRIDE 0x00000008
#endif
#define LINSYSCFLUSH_ADDR_BITS 0x000FFFFF
#define LINSYSCFLUSH_ADDR_S 0
#define LINSYSCFLUSH_LIMIT 0x047FFFFF
#define LINSYSCTRL_BASE 0x04800000
#define LINSYSCTRL_LIMIT 0x04FFFFFF
#define LINSYSMTABLE_BASE 0x05000000
#define LINSYSMTABLE_LIMIT 0x05FFFFFF
#define LINSYSDIRECT_BASE 0x06000000
#define LINSYSDIRECT_LIMIT 0x07FFFFFF
#define LINLOCAL_BASE 0x08000000
#define LINLOCAL_LIMIT 0x7FFFFFFF
#define LINCORE_BASE 0x80000000
#define LINCORE_LIMIT 0x87FFFFFF
#define LINCORE_CODE_BASE 0x80000000
#define LINCORE_CODE_LIMIT 0x81FFFFFF
#define LINCORE_DATA_BASE 0x82000000
#define LINCORE_DATA_LIMIT 0x83FFFFFF
/* The core can support locked icache lines in this region */
#define LINCORE_ICACHE_BASE 0x84000000
#define LINCORE_ICACHE_LIMIT 0x85FFFFFF
/* The core can support locked dcache lines in this region */
#define LINCORE_DCACHE_BASE 0x86000000
#define LINCORE_DCACHE_LIMIT 0x87FFFFFF
#define LINGLOBAL_BASE 0x88000000
#define LINGLOBAL_LIMIT 0xFFFDFFFF
/*
* CHIP Core Register Map
* ----------------------
*/
#define CORE_HWBASE 0x04800000
#define PRIV_HWBASE 0x04810000
#define TRIG_HWBASE 0x04820000
#define SYSC_HWBASE 0x04830000
/*****************************************************************************
* INTER-THREAD KICK REGISTERS FOR SOFTWARE EVENT GENERATION
****************************************************************************/
/*
* These values define memory mapped registers that can be used to supply
* kicks to threads that service arbitrary software events.
*/
#define T0KICK 0x04800800 /* Background kick 0 */
#define TXXKICK_MAX 0xFFFF /* Maximum kicks */
#define TnXKICK_STRIDE 0x00001000 /* Thread scale value */
#define TnXKICK_STRIDE_S 12
#define T0KICKI 0x04800808 /* Interrupt kick 0 */
#define TXIKICK_OFFSET 0x00000008 /* Int level offset value */
#define T1KICK 0x04801800 /* Background kick 1 */
#define T1KICKI 0x04801808 /* Interrupt kick 1 */
#define T2KICK 0x04802800 /* Background kick 2 */
#define T2KICKI 0x04802808 /* Interrupt kick 2 */
#define T3KICK 0x04803800 /* Background kick 3 */
#define T3KICKI 0x04803808 /* Interrupt kick 3 */
/*****************************************************************************
* GLOBAL REGISTER ACCESS RESOURCES
****************************************************************************/
/*
* These values define memory mapped registers that allow access to the
* internal state of all threads in order to allow global set-up of thread
* state and external handling of thread events, errors, or debugging.
*
* The actual unit and register index values needed to access individul
* registers are chip specific see - METAC_TXUXX_VALUES in metac_x_y.h.
* However two C array initialisers TXUXX_MASKS and TGUXX_MASKS will always be
* defined to allow arbitrary loading, display, and saving of all valid
* register states without detailed knowledge of their purpose - TXUXX sets
* bits for all valid registers and TGUXX sets bits for the sub-set which are
* global.
*/
#define T0UCTREG0 0x04800000 /* Access to all CT regs */
#define TnUCTRX_STRIDE 0x00001000 /* Thread scale value */
#define TXUCTREGn_STRIDE 0x00000008 /* Register scale value */
#define TXUXXRXDT 0x0480FFF0 /* Data to/from any threads reg */
#define TXUXXRXRQ 0x0480FFF8
#define TXUXXRXRQ_DREADY_BIT 0x80000000 /* Poll for done */
#define TXUXXRXRQ_DSPEXT_BIT 0x00020000 /* Addr DSP Regs */
#define TXUXXRXRQ_RDnWR_BIT 0x00010000 /* Set for read */
#define TXUXXRXRQ_TX_BITS 0x00003000 /* Thread number */
#define TXUXXRXRQ_TX_S 12
#define TXUXXRXRQ_RX_BITS 0x000001F0 /* Register num */
#define TXUXXRXRQ_RX_S 4
#define TXUXXRXRQ_DSPRARD0 0 /* DSP RAM A Read Pointer 0 */
#define TXUXXRXRQ_DSPRARD1 1 /* DSP RAM A Read Pointer 1 */
#define TXUXXRXRQ_DSPRAWR0 2 /* DSP RAM A Write Pointer 0 */
#define TXUXXRXRQ_DSPRAWR2 3 /* DSP RAM A Write Pointer 1 */
#define TXUXXRXRQ_DSPRBRD0 4 /* DSP RAM B Read Pointer 0 */
#define TXUXXRXRQ_DSPRBRD1 5 /* DSP RAM B Read Pointer 1 */
#define TXUXXRXRQ_DSPRBWR0 6 /* DSP RAM B Write Pointer 0 */
#define TXUXXRXRQ_DSPRBWR1 7 /* DSP RAM B Write Pointer 1 */
#define TXUXXRXRQ_DSPRARINC0 8 /* DSP RAM A Read Increment 0 */
#define TXUXXRXRQ_DSPRARINC1 9 /* DSP RAM A Read Increment 1 */
#define TXUXXRXRQ_DSPRAWINC0 10 /* DSP RAM A Write Increment 0 */
#define TXUXXRXRQ_DSPRAWINC1 11 /* DSP RAM A Write Increment 1 */
#define TXUXXRXRQ_DSPRBRINC0 12 /* DSP RAM B Read Increment 0 */
#define TXUXXRXRQ_DSPRBRINC1 13 /* DSP RAM B Read Increment 1 */
#define TXUXXRXRQ_DSPRBWINC0 14 /* DSP RAM B Write Increment 0 */
#define TXUXXRXRQ_DSPRBWINC1 15 /* DSP RAM B Write Increment 1 */
#define TXUXXRXRQ_ACC0L0 16 /* Accumulator 0 bottom 32-bits */
#define TXUXXRXRQ_ACC1L0 17 /* Accumulator 1 bottom 32-bits */
#define TXUXXRXRQ_ACC2L0 18 /* Accumulator 2 bottom 32-bits */
#define TXUXXRXRQ_ACC3L0 19 /* Accumulator 3 bottom 32-bits */
#define TXUXXRXRQ_ACC0HI 20 /* Accumulator 0 top 8-bits */
#define TXUXXRXRQ_ACC1HI 21 /* Accumulator 1 top 8-bits */
#define TXUXXRXRQ_ACC2HI 22 /* Accumulator 2 top 8-bits */
#define TXUXXRXRQ_ACC3HI 23 /* Accumulator 3 top 8-bits */
#define TXUXXRXRQ_UXX_BITS 0x0000000F /* Unit number */
#define TXUXXRXRQ_UXX_S 0
/*****************************************************************************
* PRIVILEGE CONTROL VALUES FOR MEMORY MAPPED RESOURCES
****************************************************************************/
/*
* These values define memory mapped registers that give control over and
* the privilege required to access other memory mapped resources. These
* registers themselves always require privilege to update them.
*/
#define TXPRIVREG_STRIDE 0x8 /* Delta between per-thread regs */
#define TXPRIVREG_STRIDE_S 3
/*
* Each bit 0 to 15 defines privilege required to access internal register
* regions 0x04800000 to 0x048FFFFF in 64k chunks
*/
#define T0PIOREG 0x04810100
#define T1PIOREG 0x04810108
#define T2PIOREG 0x04810110
#define T3PIOREG 0x04810118
/*
* Each bit 0 to 31 defines privilege required to use the pair of
* system events implemented as writee in the regions 0x04000000 to
* 0x04000FFF in 2*64 byte chunks.
*/
#define T0PSYREG 0x04810180
#define T1PSYREG 0x04810188
#define T2PSYREG 0x04810190
#define T3PSYREG 0x04810198
/*
* CHIP PRIV CONTROLS
* ------------------
*/
/* The TXPIOREG register holds a bit mask directly mappable to
corresponding addresses in the range 0x04800000 to 049FFFFF */
#define TXPIOREG_ADDR_BITS 0x1F0000 /* Up to 32x64K bytes */
#define TXPIOREG_ADDR_S 16
/* Hence based on the _HWBASE values ... */
#define TXPIOREG_CORE_BIT (1<<((0x04800000>>16)&0x1F))
#define TXPIOREG_PRIV_BIT (1<<((0x04810000>>16)&0x1F))
#define TXPIOREG_TRIG_BIT (1<<((0x04820000>>16)&0x1F))
#define TXPIOREG_SYSC_BIT (1<<((0x04830000>>16)&0x1F))
#define TXPIOREG_WRC_BIT 0x00080000 /* Wr combiner reg priv */
#define TXPIOREG_LOCALBUS_RW_BIT 0x00040000 /* Local bus rd/wr priv */
#define TXPIOREG_SYSREGBUS_RD_BIT 0x00020000 /* Sys reg bus write priv */
#define TXPIOREG_SYSREGBUS_WR_BIT 0x00010000 /* Sys reg bus read priv */
/* CORE region privilege controls */
#define T0PRIVCORE 0x04800828
#define TXPRIVCORE_TXBKICK_BIT 0x001 /* Background kick priv */
#define TXPRIVCORE_TXIKICK_BIT 0x002 /* Interrupt kick priv */
#define TXPRIVCORE_TXAMAREGX_BIT 0x004 /* TXAMAREG4|5|6 priv */
#define TnPRIVCORE_STRIDE 0x00001000
#define T0PRIVSYSR 0x04810000
#define TnPRIVSYSR_STRIDE 0x00000008
#define TnPRIVSYSR_STRIDE_S 3
#define TXPRIVSYSR_CFLUSH_BIT 0x01
#define TXPRIVSYSR_MTABLE_BIT 0x02
#define TXPRIVSYSR_DIRECT_BIT 0x04
#ifdef METAC_1_2
#define TXPRIVSYSR_ALL_BITS 0x07
#else
#define TXPRIVSYSR_CORE_BIT 0x08
#define TXPRIVSYSR_CORECODE_BIT 0x10
#define TXPRIVSYSR_ALL_BITS 0x1F
#endif
#define T1PRIVSYSR 0x04810008
#define T2PRIVSYSR 0x04810010
#define T3PRIVSYSR 0x04810018
/*****************************************************************************
* H/W TRIGGER STATE/LEVEL REGISTERS AND H/W TRIGGER VECTORS
****************************************************************************/
/*
* These values define memory mapped registers that give control over and
* the state of hardware trigger sources both external to the META processor
* and internal to it.
*/
#define HWSTATMETA 0x04820000 /* Hardware status/clear META trig */
#define HWSTATMETA_T0HALT_BITS 0xF
#define HWSTATMETA_T0HALT_S 0
#define HWSTATMETA_T0BHALT_BIT 0x1 /* Background HALT */
#define HWSTATMETA_T0IHALT_BIT 0x2 /* Interrupt HALT */
#define HWSTATMETA_T0PHALT_BIT 0x4 /* PF/RO Memory HALT */
#define HWSTATMETA_T0AMATR_BIT 0x8 /* AMA trigger */
#define HWSTATMETA_TnINT_S 4 /* Shift by (thread*4) */
#define HWSTATEXT 0x04820010 /* H/W status/clear external trigs 0-31 */
#define HWSTATEXT2 0x04820018 /* H/W status/clear external trigs 32-63 */
#define HWSTATEXT4 0x04820020 /* H/W status/clear external trigs 64-95 */
#define HWSTATEXT6 0x04820028 /* H/W status/clear external trigs 96-128 */
#define HWLEVELEXT 0x04820030 /* Edge/Level type of external trigs 0-31 */
#define HWLEVELEXT2 0x04820038 /* Edge/Level type of external trigs 32-63 */
#define HWLEVELEXT4 0x04820040 /* Edge/Level type of external trigs 64-95 */
#define HWLEVELEXT6 0x04820048 /* Edge/Level type of external trigs 96-128 */
#define HWLEVELEXT_XXX_LEVEL 1 /* Level sense logic in HWSTATEXTn */
#define HWLEVELEXT_XXX_EDGE 0
#define HWMASKEXT 0x04820050 /* Enable/disable of external trigs 0-31 */
#define HWMASKEXT2 0x04820058 /* Enable/disable of external trigs 32-63 */
#define HWMASKEXT4 0x04820060 /* Enable/disable of external trigs 64-95 */
#define HWMASKEXT6 0x04820068 /* Enable/disable of external trigs 96-128 */
#define T0VECINT_BHALT 0x04820500 /* Background HALT trigger vector */
#define TXVECXXX_BITS 0xF /* Per-trigger vector vals 0,1,4-15 */
#define TXVECXXX_S 0
#define T0VECINT_IHALT 0x04820508 /* Interrupt HALT */
#define T0VECINT_PHALT 0x04820510 /* PF/RO memory fault */
#define T0VECINT_AMATR 0x04820518 /* AMA trigger */
#define TnVECINT_STRIDE 0x00000020 /* Per thread stride */
#define HWVEC0EXT 0x04820700 /* Vectors for external triggers 0-31 */
#define HWVEC20EXT 0x04821700 /* Vectors for external triggers 32-63 */
#define HWVEC40EXT 0x04822700 /* Vectors for external triggers 64-95 */
#define HWVEC60EXT 0x04823700 /* Vectors for external triggers 96-127 */
#define HWVECnEXT_STRIDE 0x00000008 /* Per trigger stride */
#define HWVECnEXT_DEBUG 0x1 /* Redirect trigger to debug i/f */
/*
* CORE HWCODE-BREAKPOINT REGISTERS/VALUES
* ---------------------------------------
*/
#define CODEB0ADDR 0x0480FF00 /* Address specifier */
#define CODEBXADDR_MATCHX_BITS 0xFFFFFFFC
#define CODEBXADDR_MATCHX_S 2
#define CODEB0CTRL 0x0480FF08 /* Control */
#define CODEBXCTRL_MATEN_BIT 0x80000000 /* Match 'Enable' */
#define CODEBXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */
#define CODEBXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */
#define CODEBXCTRL_HITC_S 16
#define CODEBXHITC_NEXT 0xFF /* Next 'hit' will trigger */
#define CODEBXHITC_HIT1 0x00 /* No 'hits' after trigger */
#define CODEBXCTRL_MMASK_BITS 0x0000FFFC /* Mask ADDR_MATCH bits */
#define CODEBXCTRL_MMASK_S 2
#define CODEBXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */
#define CODEBXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */
#define CODEBnXXXX_STRIDE 0x00000010 /* Stride between CODEB reg sets */
#define CODEBnXXXX_STRIDE_S 4
#define CODEBnXXXX_LIMIT 3 /* Sets 0-3 */
/*
* CORE DATA-WATCHPOINT REGISTERS/VALUES
* -------------------------------------
*/
#define DATAW0ADDR 0x0480FF40 /* Address specifier */
#define DATAWXADDR_MATCHR_BITS 0xFFFFFFF8
#define DATAWXADDR_MATCHR_S 3
#define DATAWXADDR_MATCHW_BITS 0xFFFFFFFF
#define DATAWXADDR_MATCHW_S 0
#define DATAW0CTRL 0x0480FF48 /* Control */
#define DATAWXCTRL_MATRD_BIT 0x80000000 /* Match 'Read' */
#ifndef METAC_1_2
#define DATAWXCTRL_MATNOTTX_BIT 0x20000000 /* Invert threadn enable */
#endif
#define DATAWXCTRL_MATWR_BIT 0x40000000 /* Match 'Write' */
#define DATAWXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */
#define DATAWXCTRL_WRSIZE_BITS 0x0F000000 /* Write Match Size */
#define DATAWXCTRL_WRSIZE_S 24
#define DATAWWRSIZE_ANY 0 /* Any size transaction matches */
#define DATAWWRSIZE_8BIT 1 /* Specific sizes ... */
#define DATAWWRSIZE_16BIT 2
#define DATAWWRSIZE_32BIT 3
#define DATAWWRSIZE_64BIT 4
#define DATAWXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */
#define DATAWXCTRL_HITC_S 16
#define DATAWXHITC_NEXT 0xFF /* Next 'hit' will trigger */
#define DATAWXHITC_HIT1 0x00 /* No 'hits' after trigger */
#define DATAWXCTRL_MMASK_BITS 0x0000FFF8 /* Mask ADDR_MATCH bits */
#define DATAWXCTRL_MMASK_S 3
#define DATAWXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */
#define DATAWXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */
#define DATAW0DMATCH0 0x0480FF50 /* Write match data */
#define DATAW0DMATCH1 0x0480FF58
#define DATAW0DMASK0 0x0480FF60 /* Write match data mask */
#define DATAW0DMASK1 0x0480FF68
#define DATAWnXXXX_STRIDE 0x00000040 /* Stride between DATAW reg sets */
#define DATAWnXXXX_STRIDE_S 6
#define DATAWnXXXX_LIMIT 1 /* Sets 0,1 */
/*
* CHIP Automatic Mips Allocation control registers
* ------------------------------------------------
*/
/* CORE memory mapped AMA registers */
#define T0AMAREG4 0x04800810
#define TXAMAREG4_POOLSIZE_BITS 0x3FFFFF00
#define TXAMAREG4_POOLSIZE_S 8
#define TXAMAREG4_AVALUE_BITS 0x000000FF
#define TXAMAREG4_AVALUE_S 0
#define T0AMAREG5 0x04800818
#define TXAMAREG5_POOLC_BITS 0x07FFFFFF
#define TXAMAREG5_POOLC_S 0
#define T0AMAREG6 0x04800820
#define TXAMAREG6_DLINEDEF_BITS 0x00FFFFF0
#define TXAMAREG6_DLINEDEF_S 0
#define TnAMAREGX_STRIDE 0x00001000
/*
* Memory Management Control Unit Table Entries
* --------------------------------------------
*/
#define MMCU_ENTRY_S 4 /* -> Entry size */
#define MMCU_ENTRY_ADDR_BITS 0xFFFFF000 /* Physical address */
#define MMCU_ENTRY_ADDR_S 12 /* -> Page size */
#define MMCU_ENTRY_CWIN_BITS 0x000000C0 /* Caching 'window' selection */
#define MMCU_ENTRY_CWIN_S 6
#define MMCU_CWIN_UNCACHED 0 /* May not be memory etc. */
#define MMCU_CWIN_BURST 1 /* Cached but LRU unset */
#define MMCU_CWIN_C1SET 2 /* Cached in 1 set only */
#define MMCU_CWIN_CACHED 3 /* Fully cached */
#define MMCU_ENTRY_CACHE_BIT 0x00000080 /* Set for cached region */
#define MMCU_ECACHE1_FULL_BIT 0x00000040 /* Use all the sets */
#define MMCU_ECACHE0_BURST_BIT 0x00000040 /* Match bursts */
#define MMCU_ENTRY_SYS_BIT 0x00000010 /* Sys-coherent access required */
#define MMCU_ENTRY_WRC_BIT 0x00000008 /* Write combining allowed */
#define MMCU_ENTRY_PRIV_BIT 0x00000004 /* Privilege required */
#define MMCU_ENTRY_WR_BIT 0x00000002 /* Writes allowed */
#define MMCU_ENTRY_VAL_BIT 0x00000001 /* Entry is valid */
#ifdef METAC_2_1
/*
* Extended first-level/top table entries have extra/larger fields in later
* cores as bits 11:0 previously had no effect in such table entries.
*/
#define MMCU_E1ENT_ADDR_BITS 0xFFFFFFC0 /* Physical address */
#define MMCU_E1ENT_ADDR_S 6 /* -> resolution < page size */
#define MMCU_E1ENT_PGSZ_BITS 0x0000001E /* Page size for 2nd level */
#define MMCU_E1ENT_PGSZ_S 1
#define MMCU_E1ENT_PGSZ0_POWER 12 /* PgSz 0 -> 4K */
#define MMCU_E1ENT_PGSZ_MAX 10 /* PgSz 10 -> 4M maximum */
#define MMCU_E1ENT_MINIM_BIT 0x00000020
#endif /* METAC_2_1 */
/* MMCU control register in SYSC region */
#define MMCU_TABLE_PHYS_ADDR 0x04830010
#define MMCU_TABLE_PHYS_ADDR_BITS 0xFFFFFFFC
#ifdef METAC_2_1
#define MMCU_TABLE_PHYS_EXTEND 0x00000001 /* See below */
#endif
#define MMCU_DCACHE_CTRL_ADDR 0x04830018
#define MMCU_xCACHE_CTRL_ENABLE_BIT 0x00000001
#define MMCU_xCACHE_CTRL_PARTITION_BIT 0x00000000 /* See xCPART below */
#define MMCU_ICACHE_CTRL_ADDR 0x04830020
#ifdef METAC_2_1
/*
* Allow direct access to physical memory used to implement MMU table.
*
* Each is based on a corresponding MMCU_TnLOCAL_TABLE_PHYSn or similar
* MMCU_TnGLOBAL_TABLE_PHYSn register pair (see next).
*/
#define LINSYSMEMT0L_BASE 0x05000000
#define LINSYSMEMT0L_LIMIT 0x051FFFFF
#define LINSYSMEMTnX_STRIDE 0x00200000 /* 2MB Local per thread */
#define LINSYSMEMTnX_STRIDE_S 21
#define LINSYSMEMTXG_OFFSET 0x00800000 /* +2MB Global per thread */
#define LINSYSMEMTXG_OFFSET_S 23
#define LINSYSMEMT1L_BASE 0x05200000
#define LINSYSMEMT1L_LIMIT 0x053FFFFF
#define LINSYSMEMT2L_BASE 0x05400000
#define LINSYSMEMT2L_LIMIT 0x055FFFFF
#define LINSYSMEMT3L_BASE 0x05600000
#define LINSYSMEMT3L_LIMIT 0x057FFFFF
#define LINSYSMEMT0G_BASE 0x05800000
#define LINSYSMEMT0G_LIMIT 0x059FFFFF
#define LINSYSMEMT1G_BASE 0x05A00000
#define LINSYSMEMT1G_LIMIT 0x05BFFFFF
#define LINSYSMEMT2G_BASE 0x05C00000
#define LINSYSMEMT2G_LIMIT 0x05DFFFFF
#define LINSYSMEMT3G_BASE 0x05E00000
#define LINSYSMEMT3G_LIMIT 0x05FFFFFF
/*
* Extended MMU table functionality allows a sparse or flat table to be
* described much more efficiently than before.
*/
#define MMCU_T0LOCAL_TABLE_PHYS0 0x04830700
#define MMCU_TnX_TABLE_PHYSX_STRIDE 0x20 /* Offset per thread */
#define MMCU_TnX_TABLE_PHYSX_STRIDE_S 5
#define MMCU_TXG_TABLE_PHYSX_OFFSET 0x10 /* Global versus local */
#define MMCU_TXG_TABLE_PHYSX_OFFSET_S 4
#define MMCU_TBLPHYS0_DCCTRL_BITS 0x000000DF /* DC controls */
#define MMCU_TBLPHYS0_ENTLB_BIT 0x00000020 /* Cache in TLB */
#define MMCU_TBLPHYS0_TBLSZ_BITS 0x00000F00 /* Area supported */
#define MMCU_TBLPHYS0_TBLSZ_S 8
#define MMCU_TBLPHYS0_TBLSZ0_POWER 22 /* 0 -> 4M */
#define MMCU_TBLPHYS0_TBLSZ_MAX 9 /* 9 -> 2G */
#define MMCU_TBLPHYS0_LINBASE_BITS 0xFFC00000 /* Linear base */
#define MMCU_TBLPHYS0_LINBASE_S 22
#define MMCU_T0LOCAL_TABLE_PHYS1 0x04830708
#define MMCU_TBLPHYS1_ADDR_BITS 0xFFFFFFFC /* Physical base */
#define MMCU_TBLPHYS1_ADDR_S 2
#define MMCU_T0GLOBAL_TABLE_PHYS0 0x04830710
#define MMCU_T0GLOBAL_TABLE_PHYS1 0x04830718
#define MMCU_T1LOCAL_TABLE_PHYS0 0x04830720
#define MMCU_T1LOCAL_TABLE_PHYS1 0x04830728
#define MMCU_T1GLOBAL_TABLE_PHYS0 0x04830730
#define MMCU_T1GLOBAL_TABLE_PHYS1 0x04830738
#define MMCU_T2LOCAL_TABLE_PHYS0 0x04830740
#define MMCU_T2LOCAL_TABLE_PHYS1 0x04830748
#define MMCU_T2GLOBAL_TABLE_PHYS0 0x04830750
#define MMCU_T2GLOBAL_TABLE_PHYS1 0x04830758
#define MMCU_T3LOCAL_TABLE_PHYS0 0x04830760
#define MMCU_T3LOCAL_TABLE_PHYS1 0x04830768
#define MMCU_T3GLOBAL_TABLE_PHYS0 0x04830770
#define MMCU_T3GLOBAL_TABLE_PHYS1 0x04830778
#define MMCU_T0EBWCCTRL 0x04830640
#define MMCU_TnEBWCCTRL_BITS 0x00000007
#define MMCU_TnEBWCCTRL_S 0
#define MMCU_TnEBWCCCTRL_DISABLE_ALL 0
#define MMCU_TnEBWCCCTRL_ABIT25 1
#define MMCU_TnEBWCCCTRL_ABIT26 2
#define MMCU_TnEBWCCCTRL_ABIT27 3
#define MMCU_TnEBWCCCTRL_ABIT28 4
#define MMCU_TnEBWCCCTRL_ABIT29 5
#define MMCU_TnEBWCCCTRL_ABIT30 6
#define MMCU_TnEBWCCCTRL_ENABLE_ALL 7
#define MMCU_TnEBWCCTRL_STRIDE 8
#endif /* METAC_2_1 */
/* Registers within the SYSC register region */
#define METAC_ID 0x04830000
#define METAC_ID_MAJOR_BITS 0xFF000000
#define METAC_ID_MAJOR_S 24
#define METAC_ID_MINOR_BITS 0x00FF0000
#define METAC_ID_MINOR_S 16
#define METAC_ID_REV_BITS 0x0000FF00
#define METAC_ID_REV_S 8
#define METAC_ID_MAINT_BITS 0x000000FF
#define METAC_ID_MAINT_S 0
#ifdef METAC_2_1
/* Use of this section is strongly deprecated */
#define METAC_ID2 0x04830008
#define METAC_ID2_DESIGNER_BITS 0xFFFF0000 /* Modified by customer */
#define METAC_ID2_DESIGNER_S 16
#define METAC_ID2_MINOR2_BITS 0x00000F00 /* 3rd digit of prod rev */
#define METAC_ID2_MINOR2_S 8
#define METAC_ID2_CONFIG_BITS 0x000000FF /* Wrapper configuration */
#define METAC_ID2_CONFIG_S 0
/* Primary core identification and configuration information */
#define METAC_CORE_ID 0x04831000
#define METAC_COREID_GROUP_BITS 0xFF000000
#define METAC_COREID_GROUP_S 24
#define METAC_COREID_GROUP_METAG 0x14
#define METAC_COREID_ID_BITS 0x00FF0000
#define METAC_COREID_ID_S 16
#define METAC_COREID_ID_W32 0x10 /* >= for 32-bit pipeline */
#define METAC_COREID_CONFIG_BITS 0x0000FFFF
#define METAC_COREID_CONFIG_S 0
#define METAC_COREID_CFGCACHE_BITS 0x0007
#define METAC_COREID_CFGCACHE_S 0
#define METAC_COREID_CFGCACHE_NOM 0
#define METAC_COREID_CFGCACHE_TYPE0 1
#define METAC_COREID_CFGCACHE_NOMMU 1 /* Alias for TYPE0 */
#define METAC_COREID_CFGCACHE_NOCACHE 2
#define METAC_COREID_CFGCACHE_PRIVNOMMU 3
#define METAC_COREID_CFGDSP_BITS 0x0038
#define METAC_COREID_CFGDSP_S 3
#define METAC_COREID_CFGDSP_NOM 0
#define METAC_COREID_CFGDSP_MIN 1
#define METAC_COREID_NOFPACC_BIT 0x0040 /* Set if no FPU accum */
#define METAC_COREID_CFGFPU_BITS 0x0180
#define METAC_COREID_CFGFPU_S 7
#define METAC_COREID_CFGFPU_NOM 0
#define METAC_COREID_CFGFPU_SNGL 1
#define METAC_COREID_CFGFPU_DBL 2
#define METAC_COREID_NOAMA_BIT 0x0200 /* Set if no AMA present */
#define METAC_COREID_NOCOH_BIT 0x0400 /* Set if no Gbl coherency */
/* Core revision information */
#define METAC_CORE_REV 0x04831008
#define METAC_COREREV_DESIGN_BITS 0xFF000000
#define METAC_COREREV_DESIGN_S 24
#define METAC_COREREV_MAJOR_BITS 0x00FF0000
#define METAC_COREREV_MAJOR_S 16
#define METAC_COREREV_MINOR_BITS 0x0000FF00
#define METAC_COREREV_MINOR_S 8
#define METAC_COREREV_MAINT_BITS 0x000000FF
#define METAC_COREREV_MAINT_S 0
/* Configuration information control outside the core */
#define METAC_CORE_DESIGNER1 0x04831010 /* Arbitrary value */
#define METAC_CORE_DESIGNER2 0x04831018 /* Arbitrary value */
/* Configuration information covering presence/number of various features */
#define METAC_CORE_CONFIG2 0x04831020
#define METAC_CORECFG2_COREDBGTYPE_BITS 0x60000000 /* Core debug type */
#define METAC_CORECFG2_COREDBGTYPE_S 29
#define METAC_CORECFG2_DCSMALL_BIT 0x04000000 /* Data cache small */
#define METAC_CORECFG2_ICSMALL_BIT 0x02000000 /* Inst cache small */
#define METAC_CORECFG2_DCSZNP_BITS 0x01C00000 /* Data cache size np */
#define METAC_CORECFG2_DCSZNP_S 22
#define METAC_CORECFG2_ICSZNP_BITS 0x00380000 /* Inst cache size np */
#define METAC_CORECFG2_ICSZNP_S 19
#define METAC_CORECFG2_DCSZ_BITS 0x00070000 /* Data cache size */
#define METAC_CORECFG2_DCSZ_S 16
#define METAC_CORECFG2_xCSZ_4K 0 /* Allocated values */
#define METAC_CORECFG2_xCSZ_8K 1
#define METAC_CORECFG2_xCSZ_16K 2
#define METAC_CORECFG2_xCSZ_32K 3
#define METAC_CORECFG2_xCSZ_64K 4
#define METAC_CORE_C2ICSZ_BITS 0x0000E000 /* Inst cache size */
#define METAC_CORE_C2ICSZ_S 13
#define METAC_CORE_GBLACC_BITS 0x00001800 /* Number of Global Acc */
#define METAC_CORE_GBLACC_S 11
#define METAC_CORE_GBLDXR_BITS 0x00000700 /* 0 -> 0, R -> 2^(R-1) */
#define METAC_CORE_GBLDXR_S 8
#define METAC_CORE_GBLAXR_BITS 0x000000E0 /* 0 -> 0, R -> 2^(R-1) */
#define METAC_CORE_GBLAXR_S 5
#define METAC_CORE_RTTRACE_BIT 0x00000010
#define METAC_CORE_WATCHN_BITS 0x0000000C /* 0 -> 0, N -> 2^N */
#define METAC_CORE_WATCHN_S 2
#define METAC_CORE_BREAKN_BITS 0x00000003 /* 0 -> 0, N -> 2^N */
#define METAC_CORE_BREAKN_S 0
/* Configuration information covering presence/number of various features */
#define METAC_CORE_CONFIG3 0x04831028
#define METAC_CORECFG3_L2C_REV_ID_BITS 0x000F0000 /* Revision of L2 cache */
#define METAC_CORECFG3_L2C_REV_ID_S 16
#define METAC_CORECFG3_L2C_LINE_SIZE_BITS 0x00003000 /* L2 line size */
#define METAC_CORECFG3_L2C_LINE_SIZE_S 12
#define METAC_CORECFG3_L2C_LINE_SIZE_64B 0x0 /* 64 bytes */
#define METAC_CORECFG3_L2C_NUM_WAYS_BITS 0x00000F00 /* L2 number of ways (2^n) */
#define METAC_CORECFG3_L2C_NUM_WAYS_S 8
#define METAC_CORECFG3_L2C_SIZE_BITS 0x000000F0 /* L2 size (2^n) */
#define METAC_CORECFG3_L2C_SIZE_S 4
#define METAC_CORECFG3_L2C_UNIFIED_BIT 0x00000004 /* Unified cache: */
#define METAC_CORECFG3_L2C_UNIFIED_S 2
#define METAC_CORECFG3_L2C_UNIFIED_UNIFIED 1 /* - Unified D/I cache */
#define METAC_CORECFG3_L2C_UNIFIED_SEPARATE 0 /* - Separate D/I cache */
#define METAC_CORECFG3_L2C_MODE_BIT 0x00000002 /* Cache Mode: */
#define METAC_CORECFG3_L2C_MODE_S 1
#define METAC_CORECFG3_L2C_MODE_WRITE_BACK 1 /* - Write back */
#define METAC_CORECFG3_L2C_MODE_WRITE_THROUGH 0 /* - Write through */
#define METAC_CORECFG3_L2C_HAVE_L2C_BIT 0x00000001 /* Have L2C */
#define METAC_CORECFG3_L2C_HAVE_L2C_S 0
#endif /* METAC_2_1 */
#define SYSC_CACHE_MMU_CONFIG 0x04830028
#ifdef METAC_2_1 </