Commit 85922e54 authored by Oskar Schirmer's avatar Oskar Schirmer Committed by Thomas Gleixner
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arm: tcc8k: Choose PLL settings conforming to board layout

The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.
Signed-off-by: default avatarOskar Schirmer <>
Signed-off-by: default avatarThomas Gleixner <>
parent 30d91355
......@@ -6,6 +6,7 @@
* published by the Free Software Foundation.
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
......@@ -18,6 +19,7 @@
#include <mach/clock.h>
#include <mach/tcc-nand.h>
#include <mach/tcc8k-regs.h>
#include "common.h"
......@@ -52,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
static void __init tcc8k_map_io(void)
/* set PLL0 clock to 96MHz, adapt UART0 divisor */
__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
/* set PLL1 clock to 192MHz */
__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
/* set PLL2 clock to 48MHz */
__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
/* with CPU freq higher than 150 MHz, need extra DTCM wait */
__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
/* PLL locking time as specified */
MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
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