Commit 82d63734 authored by Russell King's avatar Russell King

ARM: bcmring: convert to sp804 clocksource

bcmring has a set of four sp804 timers incorporated, yet it has its
own copy of the sp804 code.  Convert its clocksource implementation
to the standard sp804 support code.

Cc: Jiandong Zheng <jdzheng@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ede2e234
...@@ -297,6 +297,7 @@ config ARCH_BCMRING ...@@ -297,6 +297,7 @@ config ARCH_BCMRING
depends on MMU depends on MMU
select CPU_V6 select CPU_V6
select ARM_AMBA select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_OPTIONAL_GPIOLIB
......
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/hardware/arm_timer.h> #include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -97,6 +98,35 @@ static struct clk dummy_apb_pclk = { ...@@ -97,6 +98,35 @@ static struct clk dummy_apb_pclk = {
.mode = CLK_MODE_XTAL, .mode = CLK_MODE_XTAL,
}; };
/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
#if defined(CONFIG_ARCH_FPGA11107)
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
/* slow down Linux's sense of time */
#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
#else
#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
#endif
static struct clk sp804_timer1_clk = {
.name = "sp804-timer-1",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
};
static struct clk sp804_timer3_clk = {
.name = "sp804-timer-3",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
};
static struct clk_lookup lookups[] = { static struct clk_lookup lookups[] = {
{ /* Bus clock */ { /* Bus clock */
.con_id = "apb_pclk", .con_id = "apb_pclk",
...@@ -107,6 +137,14 @@ static struct clk_lookup lookups[] = { ...@@ -107,6 +137,14 @@ static struct clk_lookup lookups[] = {
}, { /* UART1 */ }, { /* UART1 */
.dev_id = "uartb", .dev_id = "uartb",
.clk = &uart_clk, .clk = &uart_clk,
}, { /* SP804 timer 1 */
.dev_id = "sp804",
.con_id = "timer1",
.clk = &sp804_timer1_clk,
}, { /* SP804 timer 3 */
.dev_id = "sp804",
.con_id = "timer3",
.clk = &sp804_timer3_clk,
} }
}; };
...@@ -160,25 +198,10 @@ void __init bcmring_amba_init(void) ...@@ -160,25 +198,10 @@ void __init bcmring_amba_init(void)
/* /*
* Where is the timer (VA)? * Where is the timer (VA)?
*/ */
#define TIMER0_VA_BASE MM_IO_BASE_TMR #define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) #define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) #define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) #define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
#if defined(CONFIG_ARCH_FPGA11107)
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
/* slow down Linux's sense of time */
#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
#else
#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
#endif
#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ #define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
...@@ -187,10 +210,7 @@ void __init bcmring_amba_init(void) ...@@ -187,10 +210,7 @@ void __init bcmring_amba_init(void)
* *
*/ */
#define mSEC_1 1000 #define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10) #define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
/* /*
* How long is the timer interval? * How long is the timer interval?
...@@ -277,53 +297,13 @@ static struct irqaction bcmring_timer_irq = { ...@@ -277,53 +297,13 @@ static struct irqaction bcmring_timer_irq = {
.handler = bcmring_timer_interrupt, .handler = bcmring_timer_interrupt,
}; };
static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
{
return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
}
static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
{
return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
}
static struct clocksource clocksource_bcmring_timer1 = {
.name = "timer1",
.rating = 200,
.read = bcmring_get_cycles_timer1,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static struct clocksource clocksource_bcmring_timer3 = {
.name = "timer3",
.rating = 100,
.read = bcmring_get_cycles_timer3,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int __init bcmring_clocksource_init(void) static int __init bcmring_clocksource_init(void)
{ {
/* setup timer1 as free-running clocksource */ /* setup timer1 as free-running clocksource */
writel(0, TIMER1_VA_BASE + TIMER_CTRL); sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
TIMER1_VA_BASE + TIMER_CTRL);
clocksource_register_khz(&clocksource_bcmring_timer1,
TIMER1_FREQUENCY_MHZ * 1000);
/* setup timer3 as free-running clocksource */ /* setup timer3 as free-running clocksource */
writel(0, TIMER3_VA_BASE + TIMER_CTRL); sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
TIMER3_VA_BASE + TIMER_CTRL);
clocksource_register_khz(&clocksource_bcmring_timer3,
TIMER3_FREQUENCY_KHZ);
return 0; return 0;
} }
......
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