Commit 80301cdc authored by Kalle Valo's avatar Kalle Valo Committed by John W. Linville
Browse files

wl1251: use wl1251 prefix everywhere



Last we can change all code prefixes from wl12xx/WL12XX to
wl1251/WL1251.
Signed-off-by: default avatarKalle Valo <kalle.valo@nokia.com>
Reviewed-by: default avatarVidhya Govindan <vidhya.govindan@nokia.com>
Reviewed-by: default avatarLuciano Coelho <luciano.coelho@nokia.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 1e6f172f
/*
* This file is part of wl12xx
* This file is part of wl1251
*
* Copyright (c) 1998-2007 Texas Instruments Incorporated
* Copyright (C) 2008-2009 Nokia Corporation
......@@ -22,15 +22,15 @@
*
*/
#ifndef __WL12XX_H__
#define __WL12XX_H__
#ifndef __WL1251_H__
#define __WL1251_H__
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/bitops.h>
#include <net/mac80211.h>
#define DRIVER_NAME "wl12xx"
#define DRIVER_NAME "wl1251"
#define DRIVER_PREFIX DRIVER_NAME ": "
enum {
......@@ -56,25 +56,25 @@ enum {
#define DEBUG_DUMP_LIMIT 1024
#define wl12xx_error(fmt, arg...) \
#define wl1251_error(fmt, arg...) \
printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
#define wl12xx_warning(fmt, arg...) \
#define wl1251_warning(fmt, arg...) \
printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
#define wl12xx_notice(fmt, arg...) \
#define wl1251_notice(fmt, arg...) \
printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
#define wl12xx_info(fmt, arg...) \
#define wl1251_info(fmt, arg...) \
printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
#define wl12xx_debug(level, fmt, arg...) \
#define wl1251_debug(level, fmt, arg...) \
do { \
if (level & DEBUG_LEVEL) \
printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
} while (0)
#define wl12xx_dump(level, prefix, buf, len) \
#define wl1251_dump(level, prefix, buf, len) \
do { \
if (level & DEBUG_LEVEL) \
print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
......@@ -84,7 +84,7 @@ enum {
0); \
} while (0)
#define wl12xx_dump_ascii(level, prefix, buf, len) \
#define wl1251_dump_ascii(level, prefix, buf, len) \
do { \
if (level & DEBUG_LEVEL) \
print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
......@@ -94,10 +94,10 @@ enum {
true); \
} while (0)
#define WL12XX_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
#define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
CFG_BSSID_FILTER_EN)
#define WL12XX_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \
#define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \
CFG_RX_MGMT_EN | \
CFG_RX_DATA_EN | \
CFG_RX_CTL_EN | \
......@@ -105,7 +105,7 @@ enum {
CFG_RX_AUTH_EN | \
CFG_RX_ASSOC_EN)
#define WL12XX_BUSY_WORD_LEN 8
#define WL1251_BUSY_WORD_LEN 8
struct boot_attr {
u32 radio_type;
......@@ -117,13 +117,13 @@ struct boot_attr {
u32 bugfix;
};
enum wl12xx_state {
WL12XX_STATE_OFF,
WL12XX_STATE_ON,
WL12XX_STATE_PLT,
enum wl1251_state {
WL1251_STATE_OFF,
WL1251_STATE_ON,
WL1251_STATE_PLT,
};
enum wl12xx_partition_type {
enum wl1251_partition_type {
PART_DOWN,
PART_WORK,
PART_DRPW,
......@@ -131,20 +131,20 @@ enum wl12xx_partition_type {
PART_TABLE_LEN
};
struct wl12xx_partition {
struct wl1251_partition {
u32 size;
u32 start;
};
struct wl12xx_partition_set {
struct wl12xx_partition mem;
struct wl12xx_partition reg;
struct wl1251_partition_set {
struct wl1251_partition mem;
struct wl1251_partition reg;
};
struct wl12xx;
struct wl1251;
/* FIXME: I'm not sure about this structure name */
struct wl12xx_chip {
struct wl1251_chip {
u32 id;
const char *fw_filename;
......@@ -156,23 +156,23 @@ struct wl12xx_chip {
int intr_cmd_complete;
int intr_init_complete;
int (*op_upload_fw)(struct wl12xx *wl);
int (*op_upload_nvs)(struct wl12xx *wl);
int (*op_boot)(struct wl12xx *wl);
void (*op_set_ecpu_ctrl)(struct wl12xx *wl, u32 flag);
void (*op_target_enable_interrupts)(struct wl12xx *wl);
int (*op_hw_init)(struct wl12xx *wl);
int (*op_plt_init)(struct wl12xx *wl);
void (*op_tx_flush)(struct wl12xx *wl);
void (*op_fw_version)(struct wl12xx *wl);
int (*op_cmd_join)(struct wl12xx *wl, u8 bss_type, u8 dtim_interval,
int (*op_upload_fw)(struct wl1251 *wl);
int (*op_upload_nvs)(struct wl1251 *wl);
int (*op_boot)(struct wl1251 *wl);
void (*op_set_ecpu_ctrl)(struct wl1251 *wl, u32 flag);
void (*op_target_enable_interrupts)(struct wl1251 *wl);
int (*op_hw_init)(struct wl1251 *wl);
int (*op_plt_init)(struct wl1251 *wl);
void (*op_tx_flush)(struct wl1251 *wl);
void (*op_fw_version)(struct wl1251 *wl);
int (*op_cmd_join)(struct wl1251 *wl, u8 bss_type, u8 dtim_interval,
u16 beacon_interval, u8 wait);
struct wl12xx_partition_set *p_table;
struct wl1251_partition_set *p_table;
enum wl12xx_acx_int_reg *acx_reg_table;
};
struct wl12xx_stats {
struct wl1251_stats {
struct acx_statistics *fw_stats;
unsigned long fw_stats_update;
......@@ -180,7 +180,7 @@ struct wl12xx_stats {
unsigned int excessive_retries;
};
struct wl12xx_debugfs {
struct wl1251_debugfs {
struct dentry *rootdir;
struct dentry *fw_statistics;
......@@ -281,7 +281,7 @@ struct wl12xx_debugfs {
struct dentry *excessive_retries;
};
struct wl12xx {
struct wl1251 {
struct ieee80211_hw *hw;
bool mac80211_registered;
......@@ -290,7 +290,7 @@ struct wl12xx {
void (*set_power)(bool enable);
int irq;
enum wl12xx_state state;
enum wl1251_state state;
struct mutex mutex;
int physical_mem_addr;
......@@ -298,7 +298,7 @@ struct wl12xx {
int virtual_mem_addr;
int virtual_reg_addr;
struct wl12xx_chip chip;
struct wl1251_chip chip;
int cmd_box_addr;
int event_box_addr;
......@@ -385,31 +385,31 @@ struct wl12xx {
/* in dBm */
int power_level;
struct wl12xx_stats stats;
struct wl12xx_debugfs debugfs;
struct wl1251_stats stats;
struct wl1251_debugfs debugfs;
u32 buffer_32;
u32 buffer_cmd;
u8 buffer_busyword[WL12XX_BUSY_WORD_LEN];
struct wl12xx_rx_descriptor *rx_descriptor;
u8 buffer_busyword[WL1251_BUSY_WORD_LEN];
struct wl1251_rx_descriptor *rx_descriptor;
};
int wl12xx_plt_start(struct wl12xx *wl);
int wl12xx_plt_stop(struct wl12xx *wl);
int wl1251_plt_start(struct wl1251 *wl);
int wl1251_plt_stop(struct wl1251 *wl);
#define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */
#define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS
#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
#define WL12XX_DEFAULT_POWER_LEVEL 20
#define WL1251_DEFAULT_POWER_LEVEL 20
#define WL12XX_TX_QUEUE_MAX_LENGTH 20
#define WL1251_TX_QUEUE_MAX_LENGTH 20
/* Different chips need different sleep times after power on. WL1271 needs
* 200ms, WL1251 needs only 10ms. By default we use 200ms, but as soon as we
* know the chip ID, we change the sleep value in the wl12xx chip structure,
* know the chip ID, we change the sleep value in the wl1251 chip structure,
* so in subsequent power ons, we don't waste more time then needed. */
#define WL12XX_DEFAULT_POWER_ON_SLEEP 200
#define WL1251_DEFAULT_POWER_ON_SLEEP 200
#define CHIP_ID_1251_PG10 (0x7010101)
#define CHIP_ID_1251_PG11 (0x7020101)
......
This diff is collapsed.
/*
* This file is part of wl12xx
* This file is part of wl1251
*
* Copyright (c) 1998-2007 Texas Instruments Incorporated
* Copyright (C) 2008 Nokia Corporation
......@@ -22,15 +22,15 @@
*
*/
#ifndef __WL12XX_ACX_H__
#define __WL12XX_ACX_H__
#ifndef __WL1251_ACX_H__
#define __WL1251_ACX_H__
#include "wl1251.h"
#include "wl1251_cmd.h"
/* Target's information element */
struct acx_header {
struct wl12xx_cmd_header cmd;
struct wl1251_cmd_header cmd;
/* acx (or information element) header */
u16 id;
......@@ -91,15 +91,15 @@ struct acx_revision {
u32 hw_version;
} __attribute__ ((packed));
enum wl12xx_psm_mode {
enum wl1251_psm_mode {
/* Active mode */
WL12XX_PSM_CAM = 0,
WL1251_PSM_CAM = 0,
/* Power save mode */
WL12XX_PSM_PS = 1,
WL1251_PSM_PS = 1,
/* Extreme low power */
WL12XX_PSM_ELP = 2,
WL1251_PSM_ELP = 2,
};
struct acx_sleep_auth {
......@@ -1108,39 +1108,39 @@ enum {
};
int wl12xx_acx_frame_rates(struct wl12xx *wl, u8 ctrl_rate, u8 ctrl_mod,
int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod,
u8 mgt_rate, u8 mgt_mod);
int wl12xx_acx_station_id(struct wl12xx *wl);
int wl12xx_acx_default_key(struct wl12xx *wl, u8 key_id);
int wl12xx_acx_wake_up_conditions(struct wl12xx *wl, u8 wake_up_event,
int wl1251_acx_station_id(struct wl1251 *wl);
int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id);
int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event,
u8 listen_interval);
int wl12xx_acx_sleep_auth(struct wl12xx *wl, u8 sleep_auth);
int wl12xx_acx_fw_version(struct wl12xx *wl, char *buf, size_t len);
int wl12xx_acx_tx_power(struct wl12xx *wl, int power);
int wl12xx_acx_feature_cfg(struct wl12xx *wl);
int wl12xx_acx_mem_map(struct wl12xx *wl,
int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth);
int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len);
int wl1251_acx_tx_power(struct wl1251 *wl, int power);
int wl1251_acx_feature_cfg(struct wl1251 *wl);
int wl1251_acx_mem_map(struct wl1251 *wl,
struct acx_header *mem_map, size_t len);
int wl12xx_acx_data_path_params(struct wl12xx *wl,
int wl1251_acx_data_path_params(struct wl1251 *wl,
struct acx_data_path_params_resp *data_path);
int wl12xx_acx_rx_msdu_life_time(struct wl12xx *wl, u32 life_time);
int wl12xx_acx_rx_config(struct wl12xx *wl, u32 config, u32 filter);
int wl12xx_acx_pd_threshold(struct wl12xx *wl);
int wl12xx_acx_slot(struct wl12xx *wl, enum acx_slot_type slot_time);
int wl12xx_acx_group_address_tbl(struct wl12xx *wl);
int wl12xx_acx_service_period_timeout(struct wl12xx *wl);
int wl12xx_acx_rts_threshold(struct wl12xx *wl, u16 rts_threshold);
int wl12xx_acx_beacon_filter_opt(struct wl12xx *wl);
int wl12xx_acx_beacon_filter_table(struct wl12xx *wl);
int wl12xx_acx_sg_enable(struct wl12xx *wl);
int wl12xx_acx_sg_cfg(struct wl12xx *wl);
int wl12xx_acx_cca_threshold(struct wl12xx *wl);
int wl12xx_acx_bcn_dtim_options(struct wl12xx *wl);
int wl12xx_acx_aid(struct wl12xx *wl, u16 aid);
int wl12xx_acx_event_mbox_mask(struct wl12xx *wl, u32 event_mask);
int wl12xx_acx_set_preamble(struct wl12xx *wl, enum acx_preamble_type preamble);
int wl12xx_acx_cts_protect(struct wl12xx *wl,
int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time);
int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter);
int wl1251_acx_pd_threshold(struct wl1251 *wl);
int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time);
int wl1251_acx_group_address_tbl(struct wl1251 *wl);
int wl1251_acx_service_period_timeout(struct wl1251 *wl);
int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold);
int wl1251_acx_beacon_filter_opt(struct wl1251 *wl);
int wl1251_acx_beacon_filter_table(struct wl1251 *wl);
int wl1251_acx_sg_enable(struct wl1251 *wl);
int wl1251_acx_sg_cfg(struct wl1251 *wl);
int wl1251_acx_cca_threshold(struct wl1251 *wl);
int wl1251_acx_bcn_dtim_options(struct wl1251 *wl);
int wl1251_acx_aid(struct wl1251 *wl, u16 aid);
int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask);
int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble);
int wl1251_acx_cts_protect(struct wl1251 *wl,
enum acx_ctsprotect_type ctsprotect);
int wl12xx_acx_statistics(struct wl12xx *wl, struct acx_statistics *stats);
int wl12xx_acx_tsf_info(struct wl12xx *wl, u64 *mactime);
int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats);
int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime);
#endif /* __WL12XX_ACX_H__ */
#endif /* __WL1251_ACX_H__ */
/*
* This file is part of wl12xx
* This file is part of wl1251
*
* Copyright (C) 2008 Nokia Corporation
*
......@@ -28,37 +28,37 @@
#include "wl1251_spi.h"
#include "wl1251_event.h"
static void wl12xx_boot_enable_interrupts(struct wl12xx *wl)
static void wl1251_boot_enable_interrupts(struct wl1251 *wl)
{
enable_irq(wl->irq);
}
void wl12xx_boot_target_enable_interrupts(struct wl12xx *wl)
void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
{
wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
wl12xx_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}
int wl12xx_boot_soft_reset(struct wl12xx *wl)
int wl1251_boot_soft_reset(struct wl1251 *wl)
{
unsigned long timeout;
u32 boot_data;
/* perform soft reset */
wl12xx_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
/* SOFT_RESET is self clearing */
timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
while (1) {
boot_data = wl12xx_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
wl12xx_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
break;
if (time_after(jiffies, timeout)) {
/* 1.2 check pWhalBus->uSelfClearTime if the
* timeout was reached */
wl12xx_error("soft reset timeout");
wl1251_error("soft reset timeout");
return -1;
}
......@@ -66,15 +66,15 @@ int wl12xx_boot_soft_reset(struct wl12xx *wl)
}
/* disable Rx/Tx */
wl12xx_reg_write32(wl, ENABLE, 0x0);
wl1251_reg_write32(wl, ENABLE, 0x0);
/* disable auto calibration on start*/
wl12xx_reg_write32(wl, SPARE_A2, 0xffff);
wl1251_reg_write32(wl, SPARE_A2, 0xffff);
return 0;
}
int wl12xx_boot_init_seq(struct wl12xx *wl)
int wl1251_boot_init_seq(struct wl1251 *wl)
{
u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
......@@ -96,23 +96,23 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
};
/* read NVS params */
scr_pad6 = wl12xx_reg_read32(wl, SCR_PAD6);
wl12xx_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
/* read ELP_CMD */
elp_cmd = wl12xx_reg_read32(wl, ELP_CMD);
wl12xx_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
ref_freq = scr_pad6 & 0x000000FF;
wl12xx_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
wl12xx_reg_write32(wl, PLL_CAL_TIME, 0x9);
wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
/*
* PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
*/
wl12xx_reg_write32(wl, CLK_BUF_TIME, 0x6);
wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
/*
* set the clock detect feature to work in the restart wu procedure
......@@ -120,18 +120,18 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
* (ELP_CFG_MODE[13:12])
*/
tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
wl12xx_reg_write32(wl, ELP_CFG_MODE, tmp);
wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
elp_cmd |= 0x00000040;
wl12xx_reg_write32(wl, ELP_CMD, elp_cmd);
wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
/* PG 1.2: Set the BB PLL stable time to be 1000usec
* (PLL_STABLE_TIME) */
wl12xx_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
/* PG 1.2: read clock request time */
init_data = wl12xx_reg_read32(wl, CLK_REQ_TIME);
init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
/*
* PG 1.2: set the clock request time to be ref_clk_settling_time -
......@@ -141,35 +141,35 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
tmp = init_data - 0x21;
else
tmp = 0;
wl12xx_reg_write32(wl, CLK_REQ_TIME, tmp);
wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
/* set BB PLL configurations in RF AFE */
wl12xx_reg_write32(wl, 0x003058cc, 0x4B5);
wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
/* set RF_AFE_REG_5 */
wl12xx_reg_write32(wl, 0x003058d4, 0x50);
wl1251_reg_write32(wl, 0x003058d4, 0x50);
/* set RF_AFE_CTRL_REG_2 */
wl12xx_reg_write32(wl, 0x00305948, 0x11c001);
wl1251_reg_write32(wl, 0x00305948, 0x11c001);
/*
* change RF PLL and BB PLL divider for VCO clock and adjust VCO
* bais current(RF_AFE_REG_13)
*/
wl12xx_reg_write32(wl, 0x003058f4, 0x1e);
wl1251_reg_write32(wl, 0x003058f4, 0x1e);
/* set BB PLL configurations */
tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
wl12xx_reg_write32(wl, 0x00305840, tmp);
wl1251_reg_write32(wl, 0x00305840, tmp);
/* set fractional divider according to Appendix C-BB PLL
* Calculations
*/
tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
wl12xx_reg_write32(wl, 0x00305844, tmp);
wl1251_reg_write32(wl, 0x00305844, tmp);
/* set the initial data for the sigma delta */
wl12xx_reg_write32(wl, 0x00305848, 0x3039);
wl1251_reg_write32(wl, 0x00305848, 0x3039);
/*
* set the accumulator attenuation value, calibration loop1
......@@ -178,14 +178,14 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
*/
tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
wl12xx_reg_write32(wl, 0x00305854, tmp);
wl1251_reg_write32(wl, 0x00305854, tmp);
/*
* set the calibration stop time after holdoff time expires and set
* settling time HOLD_OFF_TIME_BB
*/
tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
wl12xx_reg_write32(wl, 0x00305858, tmp);
wl1251_reg_write32(wl, 0x00305858, tmp);
/*
* set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
......@@ -193,7 +193,7 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
* BB_ILOOPF[7:3]
*/
tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
wl12xx_reg_write32(wl, 0x003058f8, tmp);
wl1251_reg_write32(wl, 0x003058f8, tmp);
/*
* set regulator output voltage for n divider to
......@@ -201,10 +201,10 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
* set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
* PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
*/
wl12xx_reg_write32(wl, 0x003058f0, 0x29);
wl1251_reg_write32(wl, 0x003058f0, 0x29);
/* enable restart wakeup sequence (ELP_CMD[0]) */
wl12xx_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
/* restart sequence completed */
udelay(2000);
......@@ -212,19 +212,19 @@ int wl12xx_boot_init_seq(struct wl12xx *wl)
return 0;
}
int wl12xx_boot_run_firmware(struct wl12xx *wl)
int wl1251_boot_run_firmware(struct wl1251 *wl)
{
int loop, ret;
u32 chip_id, interrupt;
wl->chip.op_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
chip_id = wl12xx_reg_read32(wl, CHIP_ID_B);
chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
wl12xx_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
if (chip_id != wl->chip.id) {
wl12xx_error("chip id doesn't match after firmware boot");
wl1251_error("chip id doesn't match after firmware boot");
return -EIO;
}
......@@ -232,41 +232,41 @@ int wl12xx_boot_run_firmware(struct wl12xx *wl)
loop = 0;
while (loop++ < INIT_LOOP) {
udelay(INIT_LOOP_DELAY);
interrupt = wl12xx_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
if (interrupt == 0xffffffff) {
wl12xx_error("error reading hardware complete "
wl1251_error("error reading hardware complete "
"init indication");
return -EIO;
}
/* check that ACX_INTR_INIT_COMPLETE is enabled */
else if (interrupt & wl->chip.intr_init_complete) {
wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
wl->chip.intr_init_complete);
break;