Commit 7605b390 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Fix pipeline hazard.



In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 83598f1c
......@@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
_ehb
)
ASMMACRO(irq_enable_hazard,
_ehb
)
ASMMACRO(irq_disable_hazard,
_ehb
......
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