Commit 732d6913 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Stephen Boyd

clk: qcom: msm8960: fix ce3_core clk enable register

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent f073cd8a
......@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x36c4,
.enable_reg = 0x36cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_core_clk",
......
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