Commit 70883109 authored by Emmanuel Grumbach's avatar Emmanuel Grumbach Committed by David S. Miller

iwlwifi: move 3945 SCD registers to iwl-prph.h

This patch moves 3945 SCD registers to iwl-prph.h. These registers
are assigned from the periphery bus
Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarZhu Yi <yi.zhu@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 67dc320d
......@@ -805,18 +805,18 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
}
/* bypass mode */
iwl_write_prph(priv, SCD_MODE_REG, 0x2);
iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
/* RA 0 is active */
iwl_write_prph(priv, SCD_ARASTAT_REG, 0x01);
iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
/* all 6 fifo are active */
iwl_write_prph(priv, SCD_TXFACT_REG, 0x3f);
iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
iwl_write_prph(priv, SCD_SBYP_MODE_1_REG, 0x010000);
iwl_write_prph(priv, SCD_SBYP_MODE_2_REG, 0x030002);
iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004);
iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005);
iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
priv->hw_setting.shared_phys);
......@@ -1044,7 +1044,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
}
/* stop SCD */
iwl_write_prph(priv, SCD_MODE_REG, 0);
iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
/* reset TFD queues */
for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
......
......@@ -225,6 +225,18 @@
#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
#define BSM_SRAM_SIZE (1024) /* bytes */
/* ALM SCD */
/* SCD (Scheduler) */
#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
/* 4965 SCD memory mapped registers */
#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
......
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