Commit 6e19314c authored by Mike Mason's avatar Mike Mason Committed by Jesse Barnes
Browse files

PCI/powerpc: support PCIe fundamental reset



By default, the EEH framework on powerpc does what's known as a "hot
reset" during recovery of a PCI Express device.  We've found a case
where the device needs a "fundamental reset" to recover properly.  The
current PCI error recovery and EEH frameworks do not support this
distinction.

The attached patch makes changes to EEH to utilize the new bit field.
Signed-off-by: default avatarMike Mason <mmlnx@us.ibm.com>
Signed-off-by: default avatarRichard Lary <rlary@us.ibm.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent fe14acd4
......@@ -143,6 +143,7 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
dev->dev.bus = &pci_bus_type;
dev->devfn = devfn;
dev->multifunction = 0; /* maybe a lie? */
dev->needs_freset = 0; /* pcie fundamental reset required */
dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
dev->device = get_int_prop(node, "device-id", 0xffff);
......
......@@ -744,7 +744,15 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat
static void __rtas_set_slot_reset(struct pci_dn *pdn)
{
rtas_pci_slot_reset (pdn, 1);
struct pci_dev *dev = pdn->pcidev;
/* Determine type of EEH reset required by device,
* default hot reset or fundamental reset
*/
if (dev->needs_freset)
rtas_pci_slot_reset(pdn, 3);
else
rtas_pci_slot_reset(pdn, 1);
/* The PCI bus requires that the reset be held high for at least
* a 100 milliseconds. We wait a bit longer 'just in case'. */
......
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