Commit 6d272940 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (21 commits)
  libata: bump transfer chunk size if it's odd
  libata: Return proper ATA INT status in pata_bf54x driver
  pata_ali: trim trailing whitespace (fix checkpatch complaints)
  pata_isapnp: Polled devices
  pata_hpt37x: Fix cable detect bug spotted by Sergei
  pata_ali: Lots of problems still showing up with small ATAPI DMA
  pata_ali: Add Mitac 8317 and derivatives
  libata-core: List more documentation sources for reference
  ata_piix: Invalid use of writel/readl with iomap
  sata_sil24: fix sg table sizing
  pata_jmicron: fix disabled port handling in jmicron_pre_reset()
  pata_sil680: kill bogus reset code (take 2)
  ata_piix: port enable for the first SATA controller of ICH8 is 0xf not 0x3
  ata_piix: only enable the first port on apple macbook pro
  ata_piix: reorganize controller IDs
  pata_sis.c: Add Packard Bell EasyNote K5305 to laptops
  libata-scsi: be tolerant of 12-byte ATAPI commands in 16-byte CDBs
  libata: use ATA_HORKAGE_STUCK_ERR for ATAPI tape drives
  libata: workaround DRQ=1 ERR=1 for ATAPI tape drives
  libata: remove unused functions
  ...
parents f4d53ced e190222d
...@@ -119,18 +119,19 @@ enum { ...@@ -119,18 +119,19 @@ enum {
PIIX_80C_SEC = (1 << 7) | (1 << 6), PIIX_80C_SEC = (1 << 7) | (1 << 6),
/* controller IDs */ /* controller IDs */
piix_pata_33 = 0, /* PIIX4 at 33Mhz */ piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
ich_pata_33 = 1, /* ICH up to UDMA 33 only */ piix_pata_33, /* PIIX4 at 33Mhz */
ich_pata_66 = 2, /* ICH up to 66 Mhz */ ich_pata_33, /* ICH up to UDMA 33 only */
ich_pata_100 = 3, /* ICH up to UDMA 100 */ ich_pata_66, /* ICH up to 66 Mhz */
ich5_sata = 5, ich_pata_100, /* ICH up to UDMA 100 */
ich6_sata = 6, ich5_sata,
ich6_sata_ahci = 7, ich6_sata,
ich6m_sata_ahci = 8, ich6_sata_ahci,
ich8_sata_ahci = 9, ich6m_sata_ahci,
piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ ich8_sata_ahci,
tolapai_sata_ahci = 11, ich8_2port_sata,
ich9_2port_sata = 12, ich8m_apple_sata_ahci, /* locks up on second port enable */
tolapai_sata_ahci,
/* constants for mapping table */ /* constants for mapping table */
P0 = 0, /* port 0 */ P0 = 0, /* port 0 */
...@@ -239,19 +240,21 @@ static const struct pci_device_id piix_pci_tbl[] = { ...@@ -239,19 +240,21 @@ static const struct pci_device_id piix_pci_tbl[] = {
/* SATA Controller 1 IDE (ICH8) */ /* SATA Controller 1 IDE (ICH8) */
{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller 2 IDE (ICH8) */ /* SATA Controller 2 IDE (ICH8) */
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* Mobile SATA Controller IDE (ICH8M) */ /* Mobile SATA Controller IDE (ICH8M) */
{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* Mobile SATA Controller IDE (ICH8M), Apple */
{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
/* SATA Controller IDE (ICH9) */ /* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller IDE (ICH9) */ /* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9) */ /* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */ /* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */ /* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */ /* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller IDE (Tolapai) */ /* SATA Controller IDE (Tolapai) */
...@@ -427,7 +430,7 @@ static const struct piix_map_db ich6m_map_db = { ...@@ -427,7 +430,7 @@ static const struct piix_map_db ich6m_map_db = {
static const struct piix_map_db ich8_map_db = { static const struct piix_map_db ich8_map_db = {
.mask = 0x3, .mask = 0x3,
.port_enable = 0x3, .port_enable = 0xf,
.map = { .map = {
/* PM PS SM SS MAP */ /* PM PS SM SS MAP */
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
...@@ -437,7 +440,7 @@ static const struct piix_map_db ich8_map_db = { ...@@ -437,7 +440,7 @@ static const struct piix_map_db ich8_map_db = {
}, },
}; };
static const struct piix_map_db tolapai_map_db = { static const struct piix_map_db ich8_2port_map_db = {
.mask = 0x3, .mask = 0x3,
.port_enable = 0x3, .port_enable = 0x3,
.map = { .map = {
...@@ -449,7 +452,19 @@ static const struct piix_map_db tolapai_map_db = { ...@@ -449,7 +452,19 @@ static const struct piix_map_db tolapai_map_db = {
}, },
}; };
static const struct piix_map_db ich9_2port_map_db = { static const struct piix_map_db ich8m_apple_map_db = {
.mask = 0x3,
.port_enable = 0x1,
.map = {
/* PM PS SM SS MAP */
{ P0, NA, NA, NA }, /* 00b */
{ RV, RV, RV, RV },
{ P0, P2, IDE, IDE }, /* 10b */
{ RV, RV, RV, RV },
},
};
static const struct piix_map_db tolapai_map_db = {
.mask = 0x3, .mask = 0x3,
.port_enable = 0x3, .port_enable = 0x3,
.map = { .map = {
...@@ -467,11 +482,21 @@ static const struct piix_map_db *piix_map_db_table[] = { ...@@ -467,11 +482,21 @@ static const struct piix_map_db *piix_map_db_table[] = {
[ich6_sata_ahci] = &ich6_map_db, [ich6_sata_ahci] = &ich6_map_db,
[ich6m_sata_ahci] = &ich6m_map_db, [ich6m_sata_ahci] = &ich6m_map_db,
[ich8_sata_ahci] = &ich8_map_db, [ich8_sata_ahci] = &ich8_map_db,
[ich8_2port_sata] = &ich8_2port_map_db,
[ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
[tolapai_sata_ahci] = &tolapai_map_db, [tolapai_sata_ahci] = &tolapai_map_db,
[ich9_2port_sata] = &ich9_2port_map_db,
}; };
static struct ata_port_info piix_port_info[] = { static struct ata_port_info piix_port_info[] = {
[piix_pata_mwdma] = /* PIIX3 MWDMA only */
{
.sht = &piix_sht,
.flags = PIIX_PATA_FLAGS,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
.port_ops = &piix_pata_ops,
},
[piix_pata_33] = /* PIIX4 at 33MHz */ [piix_pata_33] = /* PIIX4 at 33MHz */
{ {
.sht = &piix_sht, .sht = &piix_sht,
...@@ -565,13 +590,15 @@ static struct ata_port_info piix_port_info[] = { ...@@ -565,13 +590,15 @@ static struct ata_port_info piix_port_info[] = {
.port_ops = &piix_sata_ops, .port_ops = &piix_sata_ops,
}, },
[piix_pata_mwdma] = /* PIIX3 MWDMA only */ [ich8_2port_sata] =
{ {
.sht = &piix_sht, .sht = &piix_sht,
.flags = PIIX_PATA_FLAGS, .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
PIIX_FLAG_AHCI,
.pio_mask = 0x1f, /* pio0-4 */ .pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ .mwdma_mask = 0x07, /* mwdma0-2 */
.port_ops = &piix_pata_ops, .udma_mask = ATA_UDMA6,
.port_ops = &piix_sata_ops,
}, },
[tolapai_sata_ahci] = [tolapai_sata_ahci] =
...@@ -585,7 +612,7 @@ static struct ata_port_info piix_port_info[] = { ...@@ -585,7 +612,7 @@ static struct ata_port_info piix_port_info[] = {
.port_ops = &piix_sata_ops, .port_ops = &piix_sata_ops,
}, },
[ich9_2port_sata] = [ich8m_apple_sata_ahci] =
{ {
.sht = &piix_sht, .sht = &piix_sht,
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
...@@ -595,6 +622,7 @@ static struct ata_port_info piix_port_info[] = { ...@@ -595,6 +622,7 @@ static struct ata_port_info piix_port_info[] = {
.udma_mask = ATA_UDMA6, .udma_mask = ATA_UDMA6,
.port_ops = &piix_sata_ops, .port_ops = &piix_sata_ops,
}, },
}; };
static struct pci_bits piix_enable_bits[] = { static struct pci_bits piix_enable_bits[] = {
...@@ -973,6 +1001,13 @@ static int piix_broken_suspend(void) ...@@ -973,6 +1001,13 @@ static int piix_broken_suspend(void)
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
}, },
}, },
{
.ident = "SATELLITE U205",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
},
},
{ {
.ident = "Portege M500", .ident = "Portege M500",
.matches = { .matches = {
...@@ -1086,12 +1121,12 @@ static int piix_disable_ahci(struct pci_dev *pdev) ...@@ -1086,12 +1121,12 @@ static int piix_disable_ahci(struct pci_dev *pdev)
if (!mmio) if (!mmio)
return -ENOMEM; return -ENOMEM;
tmp = readl(mmio + AHCI_GLOBAL_CTL); tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
if (tmp & AHCI_ENABLE) { if (tmp & AHCI_ENABLE) {
tmp &= ~AHCI_ENABLE; tmp &= ~AHCI_ENABLE;
writel(tmp, mmio + AHCI_GLOBAL_CTL); iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
tmp = readl(mmio + AHCI_GLOBAL_CTL); tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
if (tmp & AHCI_ENABLE) if (tmp & AHCI_ENABLE)
rc = -EIO; rc = -EIO;
} }
......
...@@ -30,6 +30,14 @@ ...@@ -30,6 +30,14 @@
* Hardware documentation available from http://www.t13.org/ and * Hardware documentation available from http://www.t13.org/ and
* http://www.sata-io.org/ * http://www.sata-io.org/
* *
* Standards documents from:
* http://www.t13.org (ATA standards, PCI DMA IDE spec)
* http://www.t10.org (SCSI MMC - for ATAPI MMC)
* http://www.sata-io.org (SATA)
* http://www.compactflash.org (CF)
* http://www.qic.org (QIC157 - Tape and DSC)
* http://www.ce-ata.org (CE-ATA: not supported)
*
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -2307,8 +2315,10 @@ int ata_dev_configure(struct ata_device *dev) ...@@ -2307,8 +2315,10 @@ int ata_dev_configure(struct ata_device *dev)
} }
if ((dev->class == ATA_DEV_ATAPI) && if ((dev->class == ATA_DEV_ATAPI) &&
(atapi_command_packet_set(id) == TYPE_TAPE)) (atapi_command_packet_set(id) == TYPE_TAPE)) {
dev->max_sectors = ATA_MAX_SECTORS_TAPE; dev->max_sectors = ATA_MAX_SECTORS_TAPE;
dev->horkage |= ATA_HORKAGE_STUCK_ERR;
}
if (dev->horkage & ATA_HORKAGE_MAX_SEC_128) if (dev->horkage & ATA_HORKAGE_MAX_SEC_128)
dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128, dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128,
...@@ -2580,81 +2590,6 @@ void sata_print_link_status(struct ata_link *link) ...@@ -2580,81 +2590,6 @@ void sata_print_link_status(struct ata_link *link)
} }
} }
/**
* __sata_phy_reset - Wake/reset a low-level SATA PHY
* @ap: SATA port associated with target SATA PHY.
*
* This function issues commands to standard SATA Sxxx
* PHY registers, to wake up the phy (and device), and
* clear any reset condition.
*
* LOCKING:
* PCI/etc. bus probe sem.
*
*/
void __sata_phy_reset(struct ata_port *ap)
{
struct ata_link *link = &ap->link;
unsigned long timeout = jiffies + (HZ * 5);
u32 sstatus;
if (ap->flags & ATA_FLAG_SATA_RESET) {
/* issue phy wake/reset */
sata_scr_write_flush(link, SCR_CONTROL, 0x301);
/* Couldn't find anything in SATA I/II specs, but
* AHCI-1.1 10.4.2 says at least 1 ms. */
mdelay(1);
}
/* phy wake/clear reset */
sata_scr_write_flush(link, SCR_CONTROL, 0x300);
/* wait for phy to become ready, if necessary */
do {
msleep(200);
sata_scr_read(link, SCR_STATUS, &sstatus);
if ((sstatus & 0xf) != 1)
break;
} while (time_before(jiffies, timeout));
/* print link status */
sata_print_link_status(link);
/* TODO: phy layer with polling, timeouts, etc. */
if (!ata_link_offline(link))
ata_port_probe(ap);
else
ata_port_disable(ap);
if (ap->flags & ATA_FLAG_DISABLED)
return;
if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
ata_port_disable(ap);
return;
}
ap->cbl = ATA_CBL_SATA;
}
/**
* sata_phy_reset - Reset SATA bus.
* @ap: SATA port associated with target SATA PHY.
*
* This function resets the SATA bus, and then probes
* the bus for devices.
*
* LOCKING:
* PCI/etc. bus probe sem.
*
*/
void sata_phy_reset(struct ata_port *ap)
{
__sata_phy_reset(ap);
if (ap->flags & ATA_FLAG_DISABLED)
return;
ata_bus_reset(ap);
}
/** /**
* ata_dev_pair - return other device on cable * ata_dev_pair - return other device on cable
* @adev: device * @adev: device
...@@ -5490,11 +5425,19 @@ fsm_start: ...@@ -5490,11 +5425,19 @@ fsm_start:
* let the EH abort the command or reset the device. * let the EH abort the command or reset the device.
*/ */
if (unlikely(status & (ATA_ERR | ATA_DF))) { if (unlikely(status & (ATA_ERR | ATA_DF))) {
ata_port_printk(ap, KERN_WARNING, "DRQ=1 with device " /* Some ATAPI tape drives forget to clear the ERR bit
"error, dev_stat 0x%X\n", status); * when doing the next command (mostly request sense).
qc->err_mask |= AC_ERR_HSM; * We ignore ERR here to workaround and proceed sending
ap->hsm_task_state = HSM_ST_ERR; * the CDB.
goto fsm_start; */
if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
ata_port_printk(ap, KERN_WARNING,
"DRQ=1 with device error, "
"dev_stat 0x%X\n", status);
qc->err_mask |= AC_ERR_HSM;
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
} }
/* Send the CDB (atapi) or the first data block (ata pio out). /* Send the CDB (atapi) or the first data block (ata pio out).
...@@ -7653,8 +7596,6 @@ EXPORT_SYMBOL_GPL(ata_dev_disable); ...@@ -7653,8 +7596,6 @@ EXPORT_SYMBOL_GPL(ata_dev_disable);
EXPORT_SYMBOL_GPL(sata_set_spd); EXPORT_SYMBOL_GPL(sata_set_spd);
EXPORT_SYMBOL_GPL(sata_link_debounce); EXPORT_SYMBOL_GPL(sata_link_debounce);
EXPORT_SYMBOL_GPL(sata_link_resume); EXPORT_SYMBOL_GPL(sata_link_resume);
EXPORT_SYMBOL_GPL(sata_phy_reset);
EXPORT_SYMBOL_GPL(__sata_phy_reset);
EXPORT_SYMBOL_GPL(ata_bus_reset); EXPORT_SYMBOL_GPL(ata_bus_reset);
EXPORT_SYMBOL_GPL(ata_std_prereset); EXPORT_SYMBOL_GPL(ata_std_prereset);
EXPORT_SYMBOL_GPL(ata_std_softreset); EXPORT_SYMBOL_GPL(ata_std_softreset);
...@@ -7725,7 +7666,6 @@ EXPORT_SYMBOL_GPL(ata_port_desc); ...@@ -7725,7 +7666,6 @@ EXPORT_SYMBOL_GPL(ata_port_desc);
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
EXPORT_SYMBOL_GPL(ata_port_pbar_desc); EXPORT_SYMBOL_GPL(ata_port_pbar_desc);
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
EXPORT_SYMBOL_GPL(ata_eng_timeout);
EXPORT_SYMBOL_GPL(ata_port_schedule_eh); EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
EXPORT_SYMBOL_GPL(ata_link_abort); EXPORT_SYMBOL_GPL(ata_link_abort);
EXPORT_SYMBOL_GPL(ata_port_abort); EXPORT_SYMBOL_GPL(ata_port_abort);
......
...@@ -559,101 +559,6 @@ void ata_port_wait_eh(struct ata_port *ap) ...@@ -559,101 +559,6 @@ void ata_port_wait_eh(struct ata_port *ap)
} }
} }
/**
* ata_qc_timeout - Handle timeout of queued command
* @qc: Command that timed out
*
* Some part of the kernel (currently, only the SCSI layer)
* has noticed that the active command on port @ap has not
* completed after a specified length of time. Handle this
* condition by disabling DMA (if necessary) and completing
* transactions, with error if necessary.
*
* This also handles the case of the "lost interrupt", where
* for some reason (possibly hardware bug, possibly driver bug)
* an interrupt was not delivered to the driver, even though the
* transaction completed successfully.
*
* TODO: kill this function once old EH is gone.
*
* LOCKING:
* Inherited from SCSI layer (none, can sleep)
*/
static void ata_qc_timeout(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
u8 host_stat = 0, drv_stat;
unsigned long flags;
DPRINTK("ENTER\n");
ap->hsm_task_state = HSM_ST_IDLE;
spin_lock_irqsave(ap->lock, flags);
switch (qc->tf.protocol) {
case ATA_PROT_DMA:
case ATA_PROT_ATAPI_DMA:
host_stat = ap->ops->bmdma_status(ap);
/* before we do anything else, clear DMA-Start bit */
ap->ops->bmdma_stop(qc);
/* fall through */
default:
ata_altstatus(ap);
drv_stat = ata_chk_status(ap);
/* ack bmdma irq events */
ap->ops->irq_clear(ap);
ata_dev_printk(qc->dev, KERN_ERR, "command 0x%x timeout, "
"stat 0x%x host_stat 0x%x\n",
qc->tf.command, drv_stat, host_stat);
/* complete taskfile transaction */
qc->err_mask |= AC_ERR_TIMEOUT;
break;
}
spin_unlock_irqrestore(ap->lock, flags);
ata_eh_qc_complete(qc);
DPRINTK("EXIT\n");
}
/**
* ata_eng_timeout - Handle timeout of queued command
* @ap: Port on which timed-out command is active
*
* Some part of the kernel (currently, only the SCSI layer)
* has noticed that the active command on port @ap has not
* completed after a specified length of time. Handle this
* condition by disabling DMA (if necessary) and completing
* transactions, with error if necessary.
*
* This also handles the case of the "lost interrupt", where
* for some reason (possibly hardware bug, possibly driver bug)
* an interrupt was not delivered to the driver, even though the
* transaction completed successfully.
*
* TODO: kill this function once old EH is gone.
*
* LOCKING:
* Inherited from SCSI layer (none, can sleep)
*/
void ata_eng_timeout(struct ata_port *ap)
{
DPRINTK("ENTER\n");
ata_qc_timeout(ata_qc_from_tag(ap, ap->link.active_tag));
DPRINTK("EXIT\n");
}
static int ata_eh_nr_in_flight(struct ata_port *ap) static int ata_eh_nr_in_flight(struct ata_port *ap)
{ {
unsigned int tag; unsigned int tag;
......
...@@ -2485,11 +2485,40 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) ...@@ -2485,11 +2485,40 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
if (!using_pio && ata_check_atapi_dma(qc)) if (!using_pio && ata_check_atapi_dma(qc))
using_pio = 1; using_pio = 1;
/* Some controller variants snoop this value for Packet transfers /* Some controller variants snoop this value for Packet
to do state machine and FIFO management. Thus we want to set it * transfers to do state machine and FIFO management. Thus we
properly, and for DMA where it is effectively meaningless */ * want to set it properly, and for DMA where it is
* effectively meaningless.
*/
nbytes = min(qc->nbytes, (unsigned int)63 * 1024); nbytes = min(qc->nbytes, (unsigned int)63 * 1024);
/* Most ATAPI devices which honor transfer chunk size don't
* behave according to the spec when odd chunk size which
* matches the transfer length is specified. If the number of
* bytes to transfer is 2n+1. According to the spec, what
* should happen is to indicate that 2n+1 is going to be
* transferred and transfer 2n+2 bytes where the last byte is
* padding.
*
* In practice, this doesn't happen. ATAPI devices first
* indicate and transfer 2n bytes and then indicate and
* transfer 2 bytes where the last byte is padding.
*
* This inconsistency confuses several controllers which
* perform PIO using DMA such as Intel AHCIs and sil3124/32.
* These controllers use actual number of transferred bytes to
* update DMA poitner and transfer of 4n+2 bytes make those
* controller push DMA pointer by 4n+4 bytes because SATA data
* FISes are aligned to 4 bytes. This causes data corruption
* and buffer overrun.
*
* Always setting nbytes to even number solves this problem
* because then ATAPI devices don't have to split data at 2n
* boundaries.
*/
if (nbytes & 0x1)
nbytes++;
qc->tf.lbam = (nbytes & 0xFF); qc->tf.lbam = (nbytes & 0xFF);
qc->tf.lbah = (nbytes >> 8); qc->tf.lbah = (nbytes >> 8);
...@@ -2869,7 +2898,8 @@ static inline int __ata_scsi_queuecmd(struct scsi_cmnd *scmd, ...@@ -2869,7 +2898,8 @@ static inline int __ata_scsi_queuecmd(struct scsi_cmnd *scmd,
xlat_func = NULL; xlat_func = NULL;
if (likely((scsi_op != ATA_16) || !atapi_passthru16)) { if (likely((scsi_op != ATA_16) || !atapi_passthru16)) {
/* relay SCSI command to ATAPI device */ /* relay SCSI command to ATAPI device */
if (unlikely(scmd->cmd_len > dev->cdb_len)) int len = COMMAND_SIZE(scsi_op);
if (unlikely(len > scmd->cmd_len || len > dev->cdb_len))
goto bad_cdb_len; goto bad_cdb_len;
xlat_func = atapi_xlat; xlat_func = atapi_xlat;
......
...@@ -63,6 +63,9 @@ static int ali_cable_override(struct pci_dev *pdev) ...@@ -63,6 +63,9 @@ static int ali_cable_override(struct pci_dev *pdev)
/* Fujitsu P2000 */ /* Fujitsu P2000 */
if (pdev->subsystem_vendor == 0x10CF && pdev->subsystem_device == 0x10AF) if (pdev->subsystem_vendor == 0x10CF && pdev->subsystem_device == 0x10AF)
return 1; return 1;
/* Mitac 8317 (Winbook-A) and relatives */
if (pdev->subsystem_vendor == 0x1071 && pdev->subsystem_device == 0x8317)
return 1;
/* Systems by DMI */ /* Systems by DMI */
if (dmi_check_system(cable_dmi_table)) if (dmi_check_system(cable_dmi_table))
return 1; return 1;
...@@ -282,6 +285,21 @@ static void ali_lock_sectors(struct ata_device *adev) ...@@ -282,6 +285,21 @@ static void ali_lock_sectors(struct ata_device *adev)
adev->max_sectors = 255; adev->max_sectors = 255;
} }
/**
* ali_check_atapi_dma - DMA check for most ALi controllers
* @adev: Device
*
* Called to decide whether commands should be sent by DMA or PIO
*/
static int ali_check_atapi_dma(struct ata_queued_cmd *qc)
{