Commit 6971e863 authored by Varadarajan Narayanan's avatar Varadarajan Narayanan Committed by Stephen Boyd

clk: qcom: Add IPQ4019 Global Clock Controller support

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: default avatarPradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: default avatarSenthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: default avatarVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: default avatarMatthew McClintock <mmcclint@codeaurora.org>
Acked-by: default avatarAndy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 92e963f5
......@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
......
......@@ -28,6 +28,14 @@ config APQ_MMCC_8084
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on ipq4019 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
config IPQ_GCC_806X
tristate "IPQ806x Global Clock Controller"
depends on COMMON_CLK_QCOM
......
......@@ -14,6 +14,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
......
/*
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
enum {
P_XO,
P_FEPLL200,
P_FEPLL500,
P_DDRPLL,
P_FEPLLWCSS2G,
P_FEPLLWCSS5G,
P_FEPLL125DLY,
P_DDRPLLAPSS,
};
static struct parent_map gcc_xo_200_500_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 1 },
{ P_FEPLL500, 2 },
};
static const char * const gcc_xo_200_500[] = {
"xo",
"fepll200",
"fepll500",
};
static struct parent_map gcc_xo_200_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 1 },
};
static const char * const gcc_xo_200[] = {
"xo",
"fepll200",
};
static struct parent_map gcc_xo_200_spi_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 2 },
};
static const char * const gcc_xo_200_spi[] = {
"xo",
"fepll200",
};
static struct parent_map gcc_xo_sdcc1_500_map[] = {
{ P_XO, 0 },
{ P_DDRPLL, 1 },
{ P_FEPLL500, 2 },
};
static const char * const gcc_xo_sdcc1_500[] = {
"xo",
"ddrpll",
"fepll500",
};
static struct parent_map gcc_xo_wcss2g_map[] = {
{ P_XO, 0 },
{ P_FEPLLWCSS2G, 1 },
};
static const char * const gcc_xo_wcss2g[] = {
"xo",
"fepllwcss2g",
};
static struct parent_map gcc_xo_wcss5g_map[] = {
{ P_XO, 0 },
{ P_FEPLLWCSS5G, 1 },
};
static const char * const gcc_xo_wcss5g[] = {
"xo",
"fepllwcss5g",
};
static struct parent_map gcc_xo_125_dly_map[] = {
{ P_XO, 0 },
{ P_FEPLL125DLY, 1 },
};
static const char * const gcc_xo_125_dly[] = {
"xo",
"fepll125dly",
};
static struct parent_map gcc_xo_ddr_500_200_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 3 },
{ P_FEPLL500, 2 },
{ P_DDRPLLAPSS, 1 },
};
static const char * const gcc_xo_ddr_500_200[] = {
"xo",
"fepll200",
"fepll500",
"ddrpllapss",
};
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
#define P_XO 0
#define FE_PLL_200 1
#define FE_PLL_500 2
#define DDRC_PLL_666 3
#define DDRC_PLL_666_SDCC 1
#define FE_PLL_125_DLY 1
#define FE_PLL_WCSS2G 1
#define FE_PLL_WCSS5G 1
static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(200000000, FE_PLL_200, 1, 0, 0),
{ }
};
static struct clk_rcg2 audio_clk_src = {
.cmd_rcgr = 0x1b000,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_audio_pwm_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "audio_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_audio_ahb_clk = {
.halt_reg = 0x1b010,
.clkr = {
.enable_reg = 0x1b010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_audio_ahb_clk",
.parent_names = (const char *[]){
"pcnoc_clk_src",
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_audio_pwm_clk = {
.halt_reg = 0x1b00C,
.clkr = {
.enable_reg = 0x1b00C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_audio_pwm_clk",
.parent_names = (const char *[]){
"audio_clk_src",
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 2, 5),
F(24000000, P_XO, 1, 1, 2),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x200c,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2008,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_names = (const char *[]){
"blsp1_qup1_i2c_apps_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3010,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_names = (const char *[]){
"blsp1_qup2_i2c_apps_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
F(960000, P_XO, 12, 1, 4),
F(4800000, P_XO, 1, 1, 10),
F(9600000, P_XO, 1, 1, 5),
F(15000000, P_XO, 1, 1, 3),
F(19200000, P_XO, 1, 2, 5),
F(24000000, P_XO, 1, 1, 2),
F(48000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_200_spi_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_names = gcc_xo_200_spi,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2004,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_names = (const char *[]){
"blsp1_qup1_spi_apps_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3014,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_names = gcc_xo_200_spi,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x300c,
.clkr = {
.enable_reg = 0x300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_names = (const char *[]){
"blsp1_qup2_spi_apps_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
F(1843200, FE_PLL_200, 1, 144, 15625),
F(3686400, FE_PLL_200, 1, 288, 15625),
F(7372800, FE_PLL_200, 1, 576, 15625),
F(14745600, FE_PLL_200, 1, 1152, 15625),
F(16000000, FE_PLL_200, 1, 2, 25),
F(24000000, P_XO, 1, 1, 2),
F(32000000, FE_PLL_200, 1, 4, 25),
F(40000000, FE_PLL_200, 1, 1, 5),
F(46400000, FE_PLL_200, 1, 29, 125),
F(48000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x2044,
.mnd_width = 16,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_names = gcc_xo_200_spi,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x203c,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_names = (const char *[]){
"blsp1_uart1_apps_clk_src",
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x3034,
.mnd_width = 16,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_names = gcc_xo_200_spi,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x302c,
.clkr = {
.enable_reg = 0x302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_names = (const char *[]){
"blsp1_uart2_apps_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(1250000, FE_PLL_200, 1, 16, 0),
F(2500000, FE_PLL_200, 1, 8, 0),
F(5000000, FE_PLL_200, 1, 4, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x8000,
.clkr = {
.enable_reg = 0x8000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_names = (const char *[]){
"gp1_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x9004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x9000,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_names = (const char *[]){
"gp2_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0xa004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_names = gcc_xo_200,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0xa000,
.clkr = {
.enable_reg = 0xa000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_names = (const char *[]){
"gp3_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(144000, P_XO, 1, 3, 240),
F(400000, P_XO, 1, 1, 0),
F(20000000, FE_PLL_500, 1, 1, 25),
F(25000000, FE_PLL_500, 1, 1, 20),
F(50000000, FE_PLL_500, 1, 1, 10),
F(100000000, FE_PLL_500, 1, 1, 5),
F(193000000, DDRC_PLL_666_SDCC, 1, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x18004,
.hid_width = 5,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
.parent_map = gcc_xo_sdcc1_500_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_sdcc1_500,
.num_parents = 3,
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_apps_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(200000000, FE_PLL_200, 1, 0, 0),
F(500000000, FE_PLL_500, 1, 0, 0),
F(626000000, DDRC_PLL_666, 1, 0, 0),
{ }
};
static struct clk_rcg2 apps_clk_src = {
.cmd_rcgr = 0x1900c,
.hid_width = 5,
.freq_tbl = ftbl_gcc_apps_clk,
.parent_map = gcc_xo_ddr_500_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apps_clk_src",
.parent_names = gcc_xo_ddr_500_200,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(100000000, FE_PLL_200, 2, 0, 0),
{ }
};
static struct clk_rcg2 apps_ahb_clk_src = {
.cmd_rcgr = 0x19014,
.hid_width = 5,
.parent_map = gcc_xo_200_500_map,
.freq_tbl = ftbl_gcc_apps_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apps_ahb_clk_src",
.parent_names = gcc_xo_200_500,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x19004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_names = (const char *[]){
"apps_ahb_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_names = (const char *[]){
"pcnoc_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcd_xo_clk = {
.halt_reg = 0x2103c,
.clkr = {
.enable_reg = 0x2103c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcd_xo_clk",
.parent_names = (const char *[]){
"xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.clkr = {
.enable_reg = 0x1300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_names = (const char *[]){
"pcnoc_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(0),